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2018-04-24arch/x86: add ENV_CACHE_AS_RAMAaron Durbin
Add ENV_CACHE_AS_RAM to indicate to compilation units if cache-as-ram is employed for that particular stage. BUG=b:72728953 Change-Id: I06dfa7afe2d967229549090d5aa95455687b0bb9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-24arch/x86/postcar: add comment clarifying reason for finalize_load()Aaron Durbin
Certain platforms need to pass different stack pointer values to postcar depending on S3 resume or not. Add comments to ease the reader in understanding the point. If different stack values weren't needed the program was already cached in stage cache with the correct value. Change-Id: I7202c62e6202a14416cb49ad5348740174747c7d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-24arch/x86: align stack on entry to x86_exception()Aaron Durbin
Entry points from assembly to C need to have the stacks aligned to 16 bytes with the newer compilers. This entry point was missed. Correct it. BUG=b:72728953 Change-Id: Idb29daf830c05fd5543c2194690364ce31b6a22c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-04-24arch/x86: prepare for having an idt in other stagesAaron Durbin
Currently the idt setup and handling is only in ramstage. In order to prepare having an exception handler in other stages move the interrupt vector entry code to its own compilation unit. vec0 and int_hand need to be global so c_start.S references will resolve at link time. BUG=b:72728953 Change-Id: I435b96d987d69fb41ea27a73e2dd634b5d6ee3d9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-20pci: Move inline PCI functions to pci_ops.hPatrick Rudolph
Move inline function where they belong to. Fixes compilation on non x86 platforms. Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25720 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-12include/memory_info.h: Change serial number field from 5 bytes to 4Raul E Rangel
dimm_info.serial had a strange contract. The SPD spec defines a 4 byte serial number. dimm_info.serial required a 4 character ascii string with a null terminator. This change makes the serial field so it matches the SPD spec. smbios.c will then translate the byte array into hex and set it on the smbios table. There were only two callers that set the serial number: * haswell/raminit.c: already does a memcpy(serial, spd->serial, 4), so it already matches the new contract. * amd_late_init.c: Previously copied the last 4 characters. Requires decoding the serial number into a byte array. google/cyan/spd/spd.c: This could be updated to pass the serial number, but it uses a hard coded spd.bin. Testing this on grunt, dmidecode now shows the full serial number: Serial Number: 00000000 BUG=b:65403853 TEST=tested on grunt Change-Id: Ifc58ad9ea4cdd2abe06a170a39b1f32680e7b299 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/25343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-11arch/riscv: Remove I/O space access functions (outb, etc.)Jonathan Neuschäfer
RISC-V does not have the kind of I/O space that x86 has. Other architectures tend to leave out these definitions as well. Change-Id: I7328dae1f1fa4ef8772750244a0b11a3fa5aa88f Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-04-09ACPI S3: Drop too early resume backupKyösti Mälkki
No longer needed as low memory backup is implemented as part of the ramstage loader, when the actual requirement of the ramstage to load is known. Change-Id: I5f5ad94bae2afef915927b9737c79431b6f75f22 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15477 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-09ioapic: extend definition name to avoid collisionMarc Jones
Change EN/DISABLED to INT_EN/DISABLED to avoid collision with other EN/DISABLE definition. Change-Id: I85b1c544d0f31340a09e18f4b36c1942ea0fa6ef Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25540 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-01x86: Increase time out for parking APs to 250msFurquan Shaikh
Change f43adf0 (intel/common/block/cpu: Change post_cpus_init after BS_DEV RESOURCES) moved post_cpus_init to BS_OS_RESUME for S3 path. This results in BSP timing out waiting for APs to be parked. This change increases the time out value for APs to be parked to 250ms. This value was chosen after running suspend-resume stress test and capturing the maximum time taken for APs to be parked for 100 iterations. Typical values observed were ~150ms. Maximum value observed was 152ms. BUG=b:76442753 TEST=Verified for 100 iterations that suspend-resume does not run into any AP park time out. Change-Id: Id3e59db4fe7a5a2fb60357b05565bba89be1e00e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-04-01arch/x86/smbios: Consider corner case of Part NumberLijian Zhao
In case of all DMI Type 17 to be empty, the strip trailing whitespace code will have a zero length Part Number entry, which will cause exception when using (len - 1) where len is zero. Add extra code to cover this corner case. BUG=b:76452395 TEST=Boot up fine with meowth platform, without this patch system will get stuck at "Create SMBIOS type 17". Change-Id: Id870c983584771dc1b60b1c99e95bbe7c0d25c4c Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/25377 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-23arch/x86/smbios: Strip trailing whitespace on DMI 17 part number.Raul E Rangel
dmidecode used to print 'HMAA51S6AMR6N-UH ' it now prints 'HMAA51S6AMR6N-UH' BUG=b:65403853 TEST=Verified using dmidecode Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia10ef434a2377e34ae7a8f733c6465c2f8ee8dfa Reviewed-on: https://review.coreboot.org/25302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-23arch/arm64/armv8/mmu: Add support for 48bit VAPatrick Rudolph
The VA space needs to be extended to support 48bit, as on Cavium SoCs the MMIO starts at 1 << 47. The following changes were done to coreboot and libpayload: * Use page table lvl 0 * Increase VA bits to 48 * Enable 256TB in MMU controller * Add additional asserts Tested on Cavium SoC and two ARM64 Chromebooks. Change-Id: I89e6a4809b6b725c3945bad7fce82b0dfee7c262 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/24970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-03-14acpi: update comment referencing ACPI IDJoel Kitching
ACPI ID for coreboot is now "BOOT" according to CL:18521. BUG=none BRANCH=master TEST=none Change-Id: I802ce284001b186f6cd8839b8c303d49f42b4d38 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/25042 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-07smbios: Extend Baseboard (or Module) Information (type2)Julien Viard de Galbert
Add more information on baseboard as described in SMBIOS Reference Specification 3.1.1. Change-Id: I9fe1c4fe70c66f8a7fcc75b93672421ae808bf1b Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-01smbios: Add option to select the enclosure typeJulien Viard de Galbert
This allows for a mainboard to change the value from its Kconfig. The default value is still SMBIOS_ENCLOSURE_DESKTOP (0x03) or SMBIOS_ENCLOSURE_LAPTOP (0x09) if SYSTEM_TYPE_LAPTOP is set. Change-Id: I35bc913af69565531831746040a0afe0cabe1c58 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-26src/arch/x86/smbios.c: Fix type 17 part numberRichard Spiegel
Some DIMMs have invalid strings when it comes to device part number (bytes 0x149-0x15c). From DDR4 SPD specs it should be ASCIIZ with unused space filled with white spaces (ASCII 0x20). Byte 20 should be 0 (ASCIIZ), all others should be ASCII. Create a test that detects invalid strings and replace invalid characters with *. If a replacement was made the output string then must be <Invalid (replaced string)>. BUG=b:73122207 TEST=Build, boot and record serial output for kahlee while injecting different strings to dmi17->PartNumber. Use code to examine SMBIOS, while testing different valid and invalid strings. Remove string injection before committing. Change-Id: Iead2a4cb14ff28d263d7214111b637e62ebd2921 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-20arch/riscv: Delegate the page fault exceptionsJonathan Neuschäfer
These exceptions were new in the Privileged Architecture spec 1.10. We need to delegate them to S-mode. Change-Id: Iec15afe9656107b9aeea1677c5b8dc7d654fa746 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-20arch/riscv: Update encoding.h and adjust related codeJonathan Neuschäfer
Update encoding.h to the version shipped with spike commit 0185d36 ("Merge pull request #165 from riscv/small_progbuf"), and copy the license header from the LICENSE file. Change-Id: I517042e5865986e88a589dc8623745f8d584d6b8 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-20arch/riscv: Pass the bootrom-provided FDT to the payloadJonathan Neuschäfer
The RISC-V boot protocol foresees that at every stage boundary (bootrom to boot loader, boot loader -> OS), register a0 contains the Hart ID and a1 contains the physical address of the Flattened Device Tree that the stage shall use. As a first step, pass the bootrom-provided FDT to the payload, unmodified. Change-Id: I468bc64a47153d564087235f1c7e2d10e3d7a658 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-20arch/riscv: Don't set up virtual memoryJonathan Neuschäfer
Due to changes in the RISC-V Privileged Architecture specification, Linux can now be started in physical memory and it will setup its own page tables. Thus we can delete most of virtual_memory.c. Change-Id: I4e69d15f8ee540d2f98c342bc4ec0c00fb48def0 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-20arch/riscv: Make RVC support configurableJonathan Neuschäfer
In order to support RISC-V processors with and without the RVC extension, configure the architecture variant (-march=...) explicitly. NOTE: Spike does support RVC, but currently doesn't select ARCH_RISCV_COMPRESSED, because coreboot's trap handler doesn't support RVC. Change-Id: Id4f69fa6b33604a5aa60fd6f6da8bd966494112f Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-20arch/riscv: Align trap_entry to 4 bytes, as required by specJonathan Neuschäfer
The RISC-V Privileged Architecture spec 1.10 requires that the address part of mtvec is four-byte aligned. The lower two bits encode a "mode" flag and should be zero for now. Add the necessary alignment directive before trap_entry. Change-Id: I83ea23e2c8f984775985ae7d61f80ad75286baaa Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-12arm64: Add read64() and write64()David Hendricks
Change-Id: I89cf4b996405af616f54cf2d9fabd4e258352b03 Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/23036 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-12armv8: Allow for ARMv8 extensions to be chosenDavid Hendricks
There are now a few architectural extensions available for ARMv8, some of which introduce instructions or other features that may be useful. This allows the user to select an extension implemented on their SoC which will set the -march option passed into the compiler. Change-Id: Ifca50dad98aab130ac04df455bac2cfb65abf82e Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/23641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-02-02arm64: Pass COREBOOT flag to ARM TF, always enable loggingJulius Werner
This patch changes the way coreboot builds ARM TF to pass the new COREBOOT flag introduced with the following pull request: https://github.com/ARM-software/arm-trusted-firmware/pull/1193 Since the new coreboot support code supports the CBMEM console, we need to always enable LOG_LEVEL INFO. Supporting platforms will parse the coreboot table to conditionally enable the serial console only if it was enabled in coreboot as well. Also remove explicit cache flushes of some BL31 parameters. Turns out we never really needed these because we already flush the whole cache when disabling the MMU, and we were already not doing it for most parameters. Change-Id: I3c52a536dc6067da1378b3f15c4a4d6cf0be7ce7 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/23558 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-02-02arch/x86/acpi/statdef.asl: Remove unnecessary whitespaceElyes HAOUAS
Change-Id: I8c49853a54fc301d39dc7c362f2085c25fad7fbd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-01-31arch/x86/acpigen: Add generator for _ROMPatrick Rudolph
Generate ACPI AML code for _ROM method. This function takes as input ROM data and ROM length. Arguments passed into _DSM method: Arg0 = Offset in Bytes Arg1 = Bytes to return Example: acpigen_write_rom(0xdeadbeef, 0x10000) AML code generated would look like: Method (_ROM, 2, NotSerialized) // _ROM: Read-Only Memory { OperationRegion (ROMS, SystemMemory, 0xdeadbeef, 0x00010000) Field (ROMS, AnyAcc, NoLock, Preserve) { Offset (0x00), RBF0, 524288 } Local0 = Arg0 Local1 = Arg1 If (Local1 > 0x1000) { Local1 = 0x1000 } If (Local0 > 0x00010000) { Return (Buffer (Local1) { 0x00 }) } If (Local0 > 0x0f000) { Local2 = 0x10000 - Local0 If (Local1 > Local2) { Local1 = Local2 } } Name (ROM1, Buffer (Local1) { 0x00 }) Local1 *= 0x08 Local0 *= 0x08 CreateField (RBF0, Local0, Local1, TMPB) ROM1 = TMPB /* \_SB_.PCI0.GFX0._ROM.TMPB */ Return (ROM1) /* \_SB_.PCI0.GFX0._ROM.ROM1 */ } Change-Id: Ie118b15257295b7133c8e585c0fd5218249dec8d Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-01-26smbios: handle DIMM of 32G or moreJulien Viard de Galbert
According to SMBIOS Reference Specification (1) section 7.18.5 Memory Device — Extended Size When the size cannot be represented in the size field, it must be set to 0x7fff and the real size stored in the extended_size field. 1: https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.1.pdf Change-Id: Idc559454c16ccd685aaaed0d60f1af69b634ea2e Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-25arch/x86: allow timestamp source to not be TSCAaron Durbin
Some x86 platforms don't have a TSC that is invariant w.r.t. rate to get accurate timestamps. As such a different timestamp is required. Therefore, allow one to specify non-TSC timestamp source and not compile in the default x86 TSC code. BUG=b:72378235,b:72170796 Change-Id: I737fcbba60665b3bc2b5864269536fda78b44d90 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-01-17cpu/intel/speedstep: Fix the PNOT ACPI methodArthur Heymans
The PNOT method never notifies the CPU to update it's _CST methods due to reliance on inexisting variable (PDCx). Add a method in the speedstep ssdt generator to notify all available CPU nodes and hook this up in this file. The cpu.asl file is moved to cpu/intel/speedstep/acpi since it now relies on code generated in the speedstep ssdt generator. CPUs not using the speedstep code never included this PNOT method so this is a logical place for this code to be. Change-Id: Ie2ba5e07b401d6f7c80c31f2bfcd9ef3ac0c1ad1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-17arch/x86/acpi_device: Provide macros for GPIO input with polarityFurquan Shaikh
Similar to ACPI_GPIO_OUTPUT, this change provides ACPI_GPIO_INPUT_* macros with ACTIVE_LOW and ACTIVE_HIGH polarity. Change-Id: I77da6ad2f04d7f7bb6774df35105bdbe963d87d3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-15Intel i82830 boards & chips: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: cpu/intel/socket_mFCBGA479 northbridge/intel/i82830 Mainboards: mainboard/rca/rm4100 mainboard/thomson/ip1000 Change-Id: I9574179516c30bb0d6a29741254293c2cc6f12e9 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-12-02arch/riscv: Remove supervisor_trap_entryJonathan Neuschäfer
coreboot only maintains a single trap entry, because it only runs in machine mode. Change-Id: I7324d9c8897d5c4e9d4784e7bc2a055890eab698 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-12-02riscv: Remove config string supportJonathan Neuschäfer
The code dealing with the old config string isn't needed anymore, because the config string has been deprecated in favor of OpenFirmware-derived devicetrees. Change-Id: I71398fb4861dbaf7eefc6e6f222bb7159798fafa Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-12-02arch/riscv: Remove the current SBI implementationJonathan Neuschäfer
This Supervisor Binary Interface, which is based on a page of code that's provided to operating systems by the M-mode software, has been superseded by a different (currently not really documented) SBI, which is based on directly executing ECALLs instructions. Thus some of our code becomes obsolete. Just rip it out until we implement the new SBI. Change-Id: Iec9c20b750f39a2b8f1553e25865bbf150605a6d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-12-02arch/riscv: Return from trap_handler instead of jumping outJonathan Neuschäfer
Change-Id: I8dbed5dbe377d3a02e58a3bc16a1ee112b28bea9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-12-02arch/riscv: Unify trap returnJonathan Neuschäfer
Change-Id: I9de0c92b3f925e8f4db00d7281222a07db68b2ae Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-23Constify struct cpu_device_id instancesJonathan Neuschäfer
There is currently no case where a struct cpu_device_id instance needs to be modified. Thus, declare all instances as const. Change-Id: I5ec7460b56d75d255b3451d76a46df76a51d6365 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-21arch/x86: Write ACPI DBG2 table only if the device has been enabledMario Scheithauer
The commit 93bbd41e (soc/intel: Enable ACPI DBG2 table generation) causes a crash on the mainboard mc_apl1. On this mainboard all internal SOC UARTs in the devicetree are switched off. As a result, no resources are allocated to the UARTs. The function find_resource() expects an existing resource. Otherwise, the CPU will stop. It should therefore not only be queried whether a device is present, but also whether it is enabled. Change-Id: I56ce44ae0cf77916fcb640f79fb8944fe33177cd Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/22552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-11-15arch/x86/acpi: Add support for writing ACPI DBG2 tableDuncan Laurie
Add a function to create an ACPI DBG2 table, which is a Microsoft ACPI extension for providing a description of the available debug interface on a board. A convenience function is provided for creating a DBG2 table with a 16550 UART based on a PCI device. This is tested by generating a device and verifying it with iasl: [000h 0000 4] Signature : "DBG2" [004h 0004 4] Table Length : 00000061 [008h 0008 1] Revision : 00 [009h 0009 1] Checksum : 3B [00Ah 0010 6] Oem ID : "CORE " [010h 0016 8] Oem Table ID : "COREBOOT" [018h 0024 4] Oem Revision : 00000000 [01Ch 0028 4] Asl Compiler ID : "CORE" [020h 0032 4] Asl Compiler Revision : 00000000 [024h 0036 4] Info Offset : 0000002C [028h 0040 4] Info Count : 00000001 [02Ch 0044 1] Revision : 00 [02Dh 0045 2] Length : 0035 [02Fh 0047 1] Register Count : 01 [030h 0048 2] Namepath Length : 000F [032h 0050 2] Namepath Offset : 0026 [034h 0052 2] OEM Data Length : 0000 [036h 0054 2] OEM Data Offset : 0000 [038h 0056 2] Port Type : 8000 [03Ah 0058 2] Port Subtype : 0000 [03Ch 0060 2] Reserved : 0000 [03Eh 0062 2] Base Address Offset : 0016 [040h 0064 2] Address Size Offset : 0022 [042h 0066 12] Base Address Register : [Generic Address Structure] [042h 0066 1] Space ID : 00 [SystemMemory] [043h 0067 1] Bit Width : 00 [044h 0068 1] Bit Offset : 00 [045h 0069 1] Encoded Access Width : 03 [DWord Access:32] [046h 0070 8] Address : 00000000FE034000 [04Eh 0078 4] Address Size : 00001000 [052h 0082 15] Namepath : "\_SB.PCI0.UAR2" Raw Table Data: Length 97 (0x61) 0000: 44 42 47 32 61 00 00 00 00 3B 43 4F 52 45 20 20 // DBG2a....;CORE 0010: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 // COREBOOT....CORE 0020: 00 00 00 00 2C 00 00 00 01 00 00 00 00 35 00 01 // ....,........5.. 0030: 0F 00 26 00 00 00 00 00 00 80 00 00 00 00 16 00 // ..&............. 0040: 22 00 00 00 00 03 00 40 03 FE 00 00 00 00 00 10 // "......@........ 0050: 00 00 5C 5F 53 42 2E 50 43 49 30 2E 55 41 52 32 // ..\_SB.PCI0.UAR2 0060: 00 // . Change-Id: I55aa3f24776b2f8aa38d7da117f422d8b8ec5479 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/22452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-10arch/x86: Add common AMD ACPI hardware definitionsMarshall Dawson
Match the corresonding Intel definitions for the ACPI register definitions. Change-Id: Ib804f4544d04fe08fefa493d75e0375de7cf9348 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-07arch/riscv: Use a separate trap stackJonathan Neuschäfer
This is the lazy solution, as explained in the comment, but it works for now. Change-Id: I46e18b6d633280d6409e42462500fbe7c6823b4d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07arch/riscv: gettimer: Don't use the config stringJonathan Neuschäfer
Accessing the config string doesn't work anymore on current versions of spike. Thus return dummy pointers until we have a better solution. Change-Id: I684fc51dc0916f2235e57e36b913d363e1cb02b1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07arch/riscv: Drop mret workaroundJonathan Neuschäfer
Our toolchain can compile mret now, and once the encoding changes, we'll have to adjust the code anyway. Change-Id: Ic37a849f65195006fa15d74f651a8aa9a9da5b5c Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07arch/riscv: mprv_read_*: Mark result as earlyclobberJonathan Neuschäfer
This fixes a case of mstatus corruption, where GCC generated code that used the same register for the mprv bit and the result. GCC inline assembly register modifiers are documented here: https://gcc.gnu.org/onlinedocs/gcc/Modifiers.html Change-Id: I2c563d171892c2e22ac96b34663aa3965553ceb3 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07arch/riscv: Fix return type of mprv_read_u64Jonathan Neuschäfer
Change-Id: I3dc12feefe5f0762e27d2ad0234371e91313c847 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-04arch/x86/acpigen: Add function to write a CPU packageNico Huber
Emits a list of CPU cores, e.g. Name (PPKG, Package (2) { \_PR.CP00, \_PR.CP01 }) Tested on Lenovo Thinkpad T500. Change-Id: I10e9ebad84343d1fb282b3fbb28f5f014f664f14 Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-03arch/x86/gdt: Move variable assignment downPaul Menzel
The Clang Static Analyzer warns about an unused assignment, when building the image for the Lenovo X60. ``` src/arch/x86/gdt.c:39:6: warning: Value stored to 'num_gdt_bytes' \ during its initialization is never read u16 num_gdt_bytes = (uintptr_t)&gdt_end - (uintptr_t)&gdt; ^~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ``` If `CONFIG_RELOCATABLE_RAMSTAGE` is selected, the function returns before the assignment is used. So, move the assignment below the if statement. Change-Id: Ibcb8bce743d8cb3625647804816fb97f937dc429 Found-by: clang version 4.0.1-6 (tags/RELEASE_401/final), Debian Sid/unstable Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/21957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 01:37:13 +0000