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AgeCommit message (Expand)Author
2016-08-15arch/riscv: Improve and refactor trap handling diagnosticsJonathan Neuschäfer
2016-08-15arch/riscv: Set the stack pointer upon trap entryJonathan Neuschäfer
2016-08-11arch/riscv: Fix the page table setup codeJonathan Neuschäfer
2016-08-11arch/riscv: Update encoding.h and dependent filesJonathan Neuschäfer
2016-08-06acpi: Generate object for coreboot table regionDuncan Laurie
2016-08-04src/arch/riscv/id.S: Don't hardcode the stringsJonathan Neuschäfer
2016-08-03ACPI: Add code to create root port entry in DMAR tableWerner Zeh
2016-08-03ACPI: Add code to include ATSR structure in DMAR tableWerner Zeh
2016-08-02arch/riscv: Add include/arch/barrier.hJonathan Neuschäfer
2016-08-01Remove non-ascii & unprintable charactersMartin Roth
2016-08-01arch/x86: Enable postcar consoleLee Leahy
2016-08-01arch/x86: Display MTRRs after MTRR update in postcarLee Leahy
2016-07-31src/arch: Capitalize CPU, RAM and ROMElyes HAOUAS
2016-07-28arch/riscv: Refactor bootblock.SJonathan Neuschäfer
2016-07-28arch/riscv: Only initialize virtual memory if it's availableJonathan Neuschäfer
2016-07-28arch/riscv: Remove spinlock code from atomic.hJonathan Neuschäfer
2016-07-27arch/x86: Add bootblock and postcar support for SOC MTRR accessLee Leahy
2016-07-26arch/x86: Generate a map file for the postcar stageLee Leahy
2016-07-26arch/x86: Organize ramstage to match other stagesLee Leahy
2016-07-26arch/x86: Move romstage files into romstage sectionLee Leahy
2016-07-26arch/x86: Move postcar stage commands into placeLee Leahy
2016-07-19arch/riscv: Enable unaligned load handlingJonathan Neuschäfer
2016-07-18arch/riscv: Remove enter_supervisorJonathan Neuschäfer
2016-07-18arch/riscv: Change all eret instructions to .word 0x30200073 (mret)Jonathan Neuschäfer
2016-07-17acpi: Change API called to write the name for ACPI_DP_TYPE_CHILDHarsha Priya
2016-07-15arch/x86: provide common Intel ACPI hardware definitionsAaron Durbin
2016-07-15arch/x86: provide common ACPI_Sx constantsAaron Durbin
2016-07-14spike-riscv: Look for the CBFS in RAMJonathan Neuschäfer
2016-07-14arch/riscv: Unconditionally start payloads in machine modeJonathan Neuschäfer
2016-07-08acpi: Change device properties to work as a treeDuncan Laurie
2016-07-07acpigen_write_package: Return pointer to package element counterDuncan Laurie
2016-07-02acpi_device: Have acpi_device_scope() use a separate bufferDuncan Laurie
2016-07-02gpio: Add support for translating gpio_t into ACPI pinDuncan Laurie
2016-06-28riscv/bootblock.S: Register machine-mode, not supervisor-mode trap handlerJonathan Neuschäfer
2016-06-28arch/riscv: Show fault PC and load address on load access faultsJonathan Neuschäfer
2016-06-28arch/riscv: Move _start to the beginning of the bootblockJonathan Neuschäfer
2016-06-24region: Add writeat and eraseat supportAntonello Dettori
2016-06-24arch/x86/smbios: Correct manufacturer IDElyes HAOUAS
2016-06-22ACPI S3: Add common recovery codeKyösti Mälkki
2016-06-22ACPI S3: Fix prohibited wakeupKyösti Mälkki
2016-06-22ACPI S3: Split support for HAVE_ACPI_RESUMEKyösti Mälkki
2016-06-22ACPI S3: Move SMP trampoline recoveryKyösti Mälkki
2016-06-22Ignore RAMTOP for MTRRsKyösti Mälkki
2016-06-21riscv-spike: Move coreboot to 0x80000000 (2GiB)Jonathan Neuschäfer
2016-06-20ACPI S3: Cleanup RSDP referenceKyösti Mälkki
2016-06-20arch/x86/smbios: Add DRAM manufacturerPatrick Rudolph
2016-06-17Move definitions of HIGH_MEMORY_SAVEKyösti Mälkki
2016-06-17Define RAMTOP for x86 onlyKyösti Mälkki
2016-06-12arch/riscv: Compile with -mcmodel=medanyJonathan Neuschäfer
2016-06-12arch/riscv: Add misc.c to bootblock/romstage to get udelay()Jonathan Neuschäfer