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2018-06-19lib: Add FIT payload supportPatrick Rudolph
* Add support for parsing and booting FIT payloads. * Build fit loader code from depthcharge. * Fix coding style. * Add Kconfig option to add compiletime support for FIT. * Add support for initrd. * Add default compat strings * Apply optional devicetree fixups using dt_apply_fixups Starting at this point the CBFS payload/ can be either SELF or FIT. Tested on Cavium SoC: Parses and loads a Linux kernel 4.16.3. Tested on Cavium SoC: Parses and loads a Linux kernel 4.15.0. Tested on Cavium SoC: Parses and loads a Linux kernel 4.1.52. Change-Id: I0f27b92a5e074966f893399eb401eb97d784850d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-06-19lib/prog_loaders: Move argument selection into selfloadPatrick Rudolph
Set the payload argument in selfload, as other (non self) payloads, are going to set a different argument. Change-Id: I994f604fc4501e0e3b00165819f796b1b8275d8c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25861 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-14arch/arm/armv7: Fix coding styleElyes HAOUAS
Change-Id: Ib5d574347373009c8021597f555e6e86c2c0c41f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-12arch/x86: Fix payload loading via bounce-bufferKyösti Mälkki
Fix regression (supposedly) after commit: 23d62dd lib/bootmem: Add more bootmem tags Without RELOCATABLE_RAMSTAGE, payload is allowed to overwrite memory regions of the running ramstage. This case is handled gracefully via a bounce-buffer implementation in arch/x86/boot.c. Change-Id: I1c9bbdb963a7210d0817a7a990a70a1e4fc03624 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-06-11selfboot: Move x86 quirk under archKyösti Mälkki
Making exceptions for some payload to be loaded near and under 1 MiB boundary sounds like a legacy 16-bit x86 BIOS thing we generally do not want under lib/. Change-Id: I8e8336a03d6f06d8f022c880a8334fe19a777f0a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-08arch/x86: Drop leftover ROMCC console supportKyösti Mälkki
Change-Id: I3e52569a34e1f7bfea8be9da91348c364ab705e1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-07arch/x86/smbios: Conditionally call SMBIOS opsNaresh G Solanki
Check whether device is enabled before calling smbios ops. BUG=None BRANCH=None TEST=Build & boot Soraka. Change-Id: I79681c10679e1de3a2d177503f29239968d0c157 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/26864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-06arch/x86: Always select RELOCATABLE_MODULESKyösti Mälkki
All boards except those with NO_RELOCATABLE_RAMSTAGE or explicit select already had this feature built. Change-Id: I838e12141243ec49c2555c09269e07476eb0cfad Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-06arch/x86: Use fixed size limit with RELOCATABLE_RAMSTAGEKyösti Mälkki
With RELOCATABLE_RAMSTAGE, variables RAMBASE and RAMTOP have no meaning any more. Change-Id: I711fe98a399177c2d3cb2a9dcdefba61031fb76d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26812 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-06arch/x86: Drop leftover ROMCC supportKyösti Mälkki
Remove the last bits of building romstage with romcc. Change-Id: I70bb1ed23a5aeb87bf7641e0b0bd604a4e622e61 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-04arch/x86: Remove unneeded includesElyes HAOUAS
Change-Id: I0b87e2b36a282c773e5f2f4a96c23aeadecb1300 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-04arch/x86: Introduce postcar_frame_add_romcache()Nico Huber
Provide a common implementation to add an MTRR entry for memory- mapped boot ROMs. Change-Id: I9fabc6b87fb36dc3d970805eb804cd950b8849d4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-31arch/x86/include/arch: Remove space after __attribute__Elyes HAOUAS
Change-Id: I7c74eff97580fbf39242f16dbdde98286678d596 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26321 Reviewed-by: Christoph Pomaska <cp_public@posteo.de> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-28arch/x86: Define HPET_ADDRESS_OVERRIDEKyösti Mälkki
Symbol defined in via/cx700 but also used elsewhere. Change-Id: I31d6043e71dea474de00f609b9609a628ecc6eb8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-28acpi: device: Walk up the tree to find identifierDuncan Laurie
Instead of just checking the immediate parent for an device name, walk up the tree to check if any parent can identify the device. This allows devices to be nested more than one level deep and still have them identified in one place by the SOC. The recursive method calling this function has been changed to handle a null return from acpi_device_name and abort instead of continuing and perhaps forming an invalid ACPI path. Change-Id: Ic17c5b6facdcb1a0ac696912867d62652b2bf18e Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/26487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-24src: Add space after 'while'Elyes HAOUAS
Change-Id: I44cdb6578f9560cf4b8b52a4958b95b65e0cd57a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-05-22Introduce bootblock self-decompressionJulius Werner
Masked ROMs are the silent killers of boot speed on devices without memory-mapped SPI flash. They often contain awfully slow SPI drivers (presumably bit-banged) that take hundreds of milliseconds to load our bootblock, and every extra kilobyte of bootblock size has a hugely disproportionate impact on boot speed. The coreboot timestamps can never show that component, but it impacts our users all the same. This patch tries to alleviate that issue a bit by allowing us to compress the bootblock with LZ4, which can cut its size down to nearly half. Of course, masked ROMs usually don't come with decompression algorithms built in, so we need to introduce a little decompression stub that can decompress the rest of the bootblock. This is done by creating a new "decompressor" stage which runs before the bootblock, but includes the compressed bootblock code in its data section. It needs to be as small as possible to get a real benefit from this approach, which means no device drivers, no console output, no exception handling, etc. Besides the decompression algorithm itself we only include the timer driver so that we can measure the boot speed impact of decompression. On ARM and ARM64 systems, we also need to give SoC code a chance to initialize the MMU, since running decompression without MMU is prohibitively slow on these architectures. This feature is implemented for ARM and ARM64 architectures for now, although most of it is architecture-independent and it should be relatively simple to port to other platforms where a masked ROM loads the bootblock into SRAM. It is also supposed to be a clean starting point from which later optimizations can hopefully cut down the decompression stub size (currently ~4K on RK3399) a bit more. NOTE: Bootblock compression is not for everyone. Possible side effects include trying to run LZ4 on CPUs that come out of reset extremely underclocked or enabling this too early in SoC bring-up and getting frustrated trying to find issues in an undebuggable environment. Ask your SoC vendor if bootblock compression is right for you. Change-Id: I0dc1cad9ae7508892e477739e743cd1afb5945e8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/26340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-21Revert "acpi: device: Walk up the tree to find identifier"Duncan Laurie
This reverts commit 8ccf59a94778fb54cc08368fb58a42b64d9489f6. This wasn't meant to be submitted yet and seems to be causing issues, just as Patrick warned me.. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I8c4b57ba92ef4e0535e4975485188114a1084f09 Reviewed-on: https://review.coreboot.org/26452 Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-18arch/x86: Increase TIMESTAMP region size to 0x200Furquan Shaikh
With the recent change 4c518e1 (timestamp: Add timestamps for TPM communication) to add more timestamps for TPM communication, now we are overflowing the TIMESTAMP region in verstage. This change increases TIMESTAMP region size to 512 bytes to accomodate this. BUG=b:79888151, b:79974682 Change-Id: I94c5403f256f0176d10ac61e9e1f60adf80db08b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-05-18acpi: device: Walk up the tree to find identifierDuncan Laurie
Instead of just checking the immediate parent for an device name, walk up the tree to check if any parent can identify the device. This allows devices to be nested more than one level deep and still have them identified in one place by the SOC. Change-Id: I9938fc20a839db91ff25e91bba08baa7421e3cd4 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/26172 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-18arch/x86/acpigen: Fix corner case in _ROM generatorPatrick Rudolph
In case the Option ROM isn't a multiple of 4KiB the last buffer was truncated to prevent a buffer overrun. But tests on nouveau showed that nouveau expects a buffer that has the requested size and is zero padded instead. Always return a buffer with requested size and zero pad the remaining bytes. Fixes nouveau on Lenovo W520 with Option ROM not being multiple of 4 KiB. Change-Id: I3f0ecc42a21945f66eb67f73e511bd516acf0fa9 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/25999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Rikken <nico@nicorikken.eu> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-05-16Revert "cbfs/payload type: Fix build warning and whitespace in name"Ronald G. Minnich
This reverts commit 717ba748366cda19b7532897a5b8d59fc2cd25d9. This breaks seabios and a few other payloads. This is not ready for use. Change-Id: I48ebe2e2628c11e935357b900d01953882cd20dd Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/26310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-15cbfs/payload type: Fix build warning and whitespace in namePaul Menzel
Currently, adding a payload to CBFS using the build system, the warning below is shown. W: Unknown type 'payload' ignored Update payload type from "simple elf" to "simple_elf" and rename the word "payload" to "simple_elf" in all Makefiles. Fixes: 4f5bed52 (cbfs: Rename CBFS_TYPE_PAYLOAD to CBFS_TYPE_SELF) Change-Id: Iccf6cc889b7ddd0c6ae04bda194fe5f9c00e495d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26240 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14pci: Fix compilation on non x86Patrick Rudolph
* Introduce pci_devfn_t on all arch * Add PCI function prototypes in arch/pci_ops.h * Remove unused pci_config_default() Change-Id: I71d6f82367e907732944ac5dfaabfa77181c5f20 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25723 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-11acpi: Add support for writing ACPI _PLD structuresDuncan Laurie
This commit adds support for writing ACPI _PLD structures that describe the physical location of a device to the OS. This can be used by any device with a physical connector, but is required when defining USB ports for the OS. A simple function is provided that generates a generic _PLD structure for USB ports based on the USB port type. Change-Id: Ic9cf1fd158eca80ead21b4725b37ab3c36b000f3 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/26171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-05-11acpi: Add support for generating ACPI _UPCDuncan Laurie
This commit adds support for writing ACPI _UPC structures that help describe USB ports for the OS. This is a simple structure format which indicates what type of port it is and whether it is connectable. It should be paired with an ACPI _PLD structure to define USB ports for the OS. Change-Id: Ide3768f60f96e9ad7f919ad3fb11d91045dc174a Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/26170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-08arch/x86/acpi_device: Add macros to define gpio with wake flagHarsha Priya
This patch adds new macros to define gpio with an option to either enable irq wake (mark it as ExclusiveAndWake flag in SSDT) or disable it (mark it as just Exclusive flag in SSDT). Change-Id: Ia71559dcae65112b75e4c789328e4a6153e922b0 Signed-off-by: Harsha Priya <harshapriya.n@intel.com> Reviewed-on: https://review.coreboot.org/25838 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08Move `pci_ops_mmconf` from arch/x86/ to device/Nico Huber
MMConf is not architecture specific. We also always provide a pci_bus_default_ops() now if MMCONF_SUPPORT is selected. Change-Id: I3f9b403da29d3fa81914cc1519710ba7d1bf2bb5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26062 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08arch/x86/acpi: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I54bebc245df6e967acd30a0b029557e23f8da529 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-04arch/x86/cpu.c: Remove unneeded headersElyes HAOUAS
Change-Id: I35fcf25906bf7fe5af133618654bb121404743fc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04arch/x86/cpu_common.c: Remove unneeded headersElyes HAOUAS
Change-Id: I4f57376138725804133059c785e89e095fd6a759 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04lib/bootmem: Add more bootmem tagsPatrick Rudolph
Introduce new bootmem tags to allow more fine grained control over buffer allocation on various platforms. The new tags are: BM_MEM_RAMSTAGE : Memory where any kind of boot firmware resides and that should not be touched by bootmem (by example: stack, TTB, program, ...). BM_MEM_PAYLOAD : Memory where any kind of payload resides and that should not be touched by bootmem. Starting with this commit all bootmem methods will no longer see memory that is used by coreboot as usable RAM. Bootmem changes: * Introduce a weak function to add platform specific memranges. * Mark memory allocated by bootmem as BM_TAG_PAYLOAD. * Assert on failures. * Add _stack and _program as BM_MEM_RAMSTAGE. ARMv7 and ARMv8 specific changes: * Add _ttb and _postram_cbfs_cache as BM_MEM_RAMSTAGE. ARMv7 specific changes: * Add _ttb_subtables as BM_MEM_RAMSTAGE. Change-Id: I0c983ce43616147c519a43edee3b61d54eadbb9a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-03pci: Add dummy file for ARM64Patrick Rudolph
Add stub files to support compiling the PCI driver on ARCH_ARM64. Change-Id: Iaff20463375d1e3ec573d9486a859a0514b0b390 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-03arch/x86: Relocate GDT in verstage, romstage, and postcarHannah Williams
In each stage keep GDT in the code region. This accommodates platforms, such as glk, that are executing out of CAR. The gdt is small and loading it is trivial so just do it unconditionally instead of introducing another Kconfig. BUG=b:78656686 Change-Id: I01ded6e9b358b23e04d92bef5263bfe8c2a5ec5a Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-05-03arch/x86: reduce complexity in assembly_entry.SAaron Durbin
Now that VBOOT_STARTS_IN_BOOTBLOCK depends on C_ENVIRONMENT_BOOTBLOCK, remove the complications in assembly_entry.S. There's no platform utilizing romcc bootblock and needing to handle verified boot after bootblock as well as not using verified boot. That combination makes things very complicated. Clean up the complication as it's not a combination that needs to be supported. BUG=b:78656686 Change-Id: Ie2960790d60ccb8d5b75dab507fe70a6563b3d34 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25968 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-02src/drivers: Add reset/enable/stop_off_ms variables to ACPI devicesShelley Chen
Some touchscreens need to adhere to certain timings during the power off sequence as well as during the power on sequence. Adding reset_off_delay_ms, enable_off_delay_ms, and stop_off_delay_ms to accommodate these devices. BUG=b:78311818 BRANCH=None TEST=./util/abuild/abuild -p none -t google/poppy -x -a Change-Id: Idb4a5dbe56eee4749d2f2b514e92c28fb2c6078f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/25882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-02pci: Fix MMCONF_SUPPORT on non x86Patrick Rudolph
Move x86 specific pci_bus_default_ops into arch/x86 folder. Fixes compilation on platforms that do neither have MMCONF_SUPPORT nor NO_MMCONF_SUPPORT (for example: all non-x86) but select PCI. Change-Id: I0991ab00c9a56b23cd012dd2b8b861f9737a9e9c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-02arch/x86: Print CPU Index and APIC ID in case of exceptionSubrata Banik
BUG=b:74436746 BRANCH=none TEST=Able to get APIC ID number for debug. Change-Id: I2d3776c9259747197a5f2410032f9b03786407fb Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-04-30lib/bootmem: Introduce custom bootmem tagsPatrick Rudolph
Introduce bootmem custom memory tags and use them instead of reusing LB_MEM tags. Use asserts in bootmem_add_range to verify parameters. Tested with uImage payload on Cavium SoC. Change-Id: I7be8fa792fc7933ca218ecd43d250d3a9c55caa6 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-04-30arm64: Add ARCH TimerT Michael Turney
SoC sdm845 uses ARCH Timer Change-Id: I45e2d4d2c16a2cded3df20d393d2b8820050ac80 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/25612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-04-30arm64: Add mmu context save/restore APIsT Michael Turney
New API required by sdm845 DDR init/training protocol TEST=build & run Change-Id: I8442442c0588dd6fb5e461b399e48a761f7bbf29 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/25818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-04-30x86/mpspec: order the I/O APICs by the APIC IdLubomir Rintel
Linux (4.16) assumes that the PIT interrupt is connected to the pin 0 of the IOAPIC[0] and panics otherwise. This might be a Linux bug. The MP Specification 1.4 does seem to mandate sequential ordering for bus entries, but not for the I/O APICs. Change-Id: Ibf823eb5b3a29e4590cba915069cdfe5f780edcd Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/25799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-30device: constify some variablesLubomir Rintel
Change-Id: I6830a65bc9cea2907f4209bb97a53ccebcbf248d Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/25873 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-27RISC-V boards: Remove PAGETABLES section from memlayout.ldJonathan Neuschäfer
RISC-V doesn't set up page tables anymore, since commit b26759d703 ("arch/riscv: Don't set up virtual memory"). Change-Id: Id1e759b63fb0bc88ab256994d3849d16814affa0 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-04-26arch/x86: remove nop padding from exception vectorsAaron Durbin
Now that assembly code isn't processing the idt gates there's no need to ensure each vector entry is the same amount of code. BUG=b:72728953 Change-Id: I2b248b26b9df36d6543163762c74622f79278961 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25765 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-26arch/x86: print cr2 value on every exceptionAaron Durbin
Even though most x86 systems don't run with paging on, it's helpful to always print it out for the ones that do without making a more complicated handler. New dump will look like the following: Unexpected Exception: 6 @ 10:7ab84be2 - Halting Code: 0 eflags: 00010006 cr2: 00000000 eax: 7abb80ec ebx: deadbeef ecx: 00000000 edx: 00000002 edi: 7abb3000 esi: 00000004 ebp: 7abb2fd8 esp: 7abb2fb0 7ab84ba0: 00 01 00 83 ec 0c 6a 39 7ab84ba8: e8 8a 02 01 00 e8 e1 08 7ab84bb0: 00 00 e8 4e 3d 00 00 59 7ab84bb8: 5b 52 50 e8 f5 3c 00 00 7ab84bc0: c7 04 24 0a 00 00 00 e8 7ab84bc8: 3c 3d 00 00 c7 04 24 80 7ab84bd0: 00 00 00 e8 5f 02 01 00 7ab84bd8: e8 1e 38 01 00 e8 7e 50 7ab84be0: 01 00 0f 0b bb 98 ec ba 7ab84be8: 7a 83 c4 10 8b 03 85 c0 7ab84bf0: 0f 84 be 00 00 00 83 78 7ab84bf8: 04 00 8d 50 08 75 0c 56 7ab84c00: 56 ff 30 52 e8 f8 fe ff 7ab84c08: ff eb 0a 51 51 ff 30 52 7ab84c10: e8 2e ff ff ff 83 c4 10 7ab84c18: 83 c3 04 eb cf 89 d8 e8 BUG=b:72728953 Change-Id: I0e87bbe776f77623ad8297f5d80167998daec6ed Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25762 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-26arch/x86: allow idt to be available to link in all stagesAaron Durbin
Add Kconfig IDT_IN_EVERY_STAGE to optionally specify having the interrupt handling code available to all stages. In order to do this the idt setup is moved to a C module. The vecX entries are made global so that a table of references to all the interrupt vector entry points can be used to dynamically initialize the idt. The ramification for ramstage is that exceptions are initialized later (lib/hardwaremain.c). Not all stages initialize exceptions when this Kconfig variable is selected, but bootblock for the C, stages using assembly_entry.S, and of course ramstage do. Anything left out just needs a call to exception_init() at the right location. BUG=b:72728953 Change-Id: I4146a040e5e43bed7ccc6cb0a7dc2271f1e7b7fa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-26arch/riscv: Store mprv bit in size_tJonathan Neuschäfer
CSRs are XLEN bits wide (i.e. the same width as general purpose registers), so size_t seems a little more correct than int. This change doesn't affect functionality because MSTATUS_MPRV already fits in 31 bits. Change-Id: I003c1b88b4493681dc9b6178ac785be330203ef5 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-04-25arch/x86: add support for cache-as-ram pagingAaron Durbin
Processors, such as glk, need to have paging enabled while in cache-as-ram mode because the front end is agressive about fetching lines into the L1I cache. If the line is dirty and in the L1D then it writes it back to "memory". However, in this case there is no backing store so the cache-as-ram data that was written back transforms to all 0xff's when read back in causing corruption. In order to mitigate the failure add x86 architecture support for enabling paging while in cache-as-ram mode. A Kconfig variable, NUM_CAR_PAGE_TABLE_PAGES, determines the number of pages to carve out for page tables within the cache-as-ram region. Additionally, the page directory pointer table is also carved out of cache-as-ram. Both areas are allocated from the persist-across-stages region of cache-as-ram so all stages utilizing cache-as-ram don't corrupt the page tables. The two paging-related areas are loaded by calling paging_enable_for_car() with the names of cbfs files to load the initial paging structures from. BUG=b:72728953 Change-Id: I7ea6e3e7be94a0ef9fd3205ce848e539bfbdcb6e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-24arch/x86: add ENV_CACHE_AS_RAMAaron Durbin
Add ENV_CACHE_AS_RAM to indicate to compilation units if cache-as-ram is employed for that particular stage. BUG=b:72728953 Change-Id: I06dfa7afe2d967229549090d5aa95455687b0bb9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
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