summaryrefslogtreecommitdiff
path: root/src/arch
AgeCommit message (Collapse)Author
2014-08-06Set armv7 up for cpu_info to work as on x86 (so threads can work)Ronald G. Minnich
On x86, cpu_info lives at the top of stack. Make the arm do that as well, as the threading model needs that and so will multicore support. As part of this change, make the stack size a power of 2. Also make it much smaller -- 2048 bytes is PLENTY for ram stage. Note that the small stack size is counterintuitive for rom stage. How can this work in rom stage, which needs a HUGE stack for lzma? The main use of STACK_SIZE has always been in ram stage; since 2002 or so it was to size per-core stacks (see, e.g., src/arch/x86/lib/c_start.S:.space CONFIG_MAX_CPUS*CONFIG_STACK_SIZE and, more recently, thread stacks. So, we define the STACK_TOP for rom and ram stage, but the STACK_SIZE has no real effect on the ROM stage (no hardware red zones on the stack) and hence we're ok with actually defining the "wrong" stack size. In fact, the coreboot_ram ldscript for armv7 sizes the stack by subtracting CONFIG_STACK_BOTTOM from CONFIG_STACK_TOP, so we replicate that arithmetic in bootblock.inc Observed stack usage in ramstage: BS: BS_PAYLOAD_LOAD times (us): entry 1 run 153887 exit 1 Jumping to boot code at 23104044 CPU0: stack: 02072800 - 02073000, lowest used address 020728d4, stack used: 1836 bytes entry = 23104044 Which means we do need 2K, not 1K. Change-Id: I1a21db87081597efe463095bfd33c89eba1d569f Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66135 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit f011097e9f2bfb2f4c1109d465be89a79a65ba3e) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6501 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-03arch/x86/Makefile.inc: trivial: fix indent of informative output about bootblockDaniele Forsi
Fixes the 4th line of this sequence: ROMCC generated/bootblock.inc GEN generated/bootblock_inc.S CC generated/bootblock.s CC generated/bootblock.o GEN generated/bootblock.ld Change-Id: Ic0704b83ec9c4191e26a94e0d69cbf4c0486ceed Signed-off-by: Daniele Forsi <dforsi@gmail.com> Reviewed-on: http://review.coreboot.org/6466 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-01armv7: add wrapper for DCCSW (data cache clean by set/way)David Hendricks
This adds a wrapper for data cache clean (without invalidate) by set/way. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I09ee1563890350a6c1d04f1b96ac5d0c042e2af2 Reviewed-on: https://gerrit.chromium.org/gerrit/66118 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit 05bc4f8564c547eacb9cc840a03b916b3c1c6001) armv7: clean but do not invalidate caches between stages This cleans the caches without invalidating them between stages. The dcache content should still be valid when the next stage begins, so we should see a small performance gain. (thanks to gabeblack for pointing this out) Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: Ie18d163f3a78e2786e9fbc7479c8bd896b8ac3aa Reviewed-on: https://gerrit.chromium.org/gerrit/66119 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit 619bfe4cf9b93847e38d03d7076beb78fbfa1d1d) armv7: Make coreboot and libpayload cache files the same This merges the difference between the ARM version of cache.c and cache.h for libpayload and coreboot. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I246d2ec98385100304266f4bb15337a8fcf8df93 Reviewed-on: https://gerrit.chromium.org/gerrit/66120 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit 0c92f694034f1e94a8aa7811251738c9dc3db2c6) ARM: Fix cache cleaning operation. There was no behavior defined for OP_DCCSW in dcache_op_set_way, so it silently did nothing. Since we started using that to clean the cache between stages and I have a change that enables caches earlier on, this was preventing booting on pit. Old-Change-Id: I3615b6569bf8de195d19d26b62f02932322b7601 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66234 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 99241468cb9dcc86fcca9266ffe72baa88a1f79f) libpayload: Fix data cache cleaning on ARM. A similar fix was made to coreboot where OP_DCCSW was silently not doing anything in dcache_op_set_way. Old-Change-Id: Ia0798aef0cd02da7d1a14b7affa05038a002ab3b Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66236 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 6f6596a182a6780a2e997ac320733722697990c5) Squashed five related commits. Change-Id: I763d42bd5dd9f58734e1e21eb7c8ce3ce2ea56ee Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6418 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-31payloads/external/SeaBIOS: Use coreboot’s serial console settingsMartin Roth
Set up the serial console on SeaBIOS to match coreboot's settings. Previously, we were just forcing it on, and setting it to 0x3f8. Change-Id: I107245c8bd1ba2cf948c6671337c6169226aaaaf Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6363 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-31armv7/exynos5420: Configure CPU cores for kernel to enable SMP.Hung-Te Lin
The SMP on Exynos 5420 requires setting a special page and entry wrappers in firmware side (SRAM) so kernel can start cores (and to switch clusters). Change-Id: I77ca98bb6cff5b13e95dd29228e4536302f0aee9 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/64770 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit 4a11c7ab78cc0811df0f88763b0af8b9f24e5433) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6405 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-30arch/x86/include/arch/interrupt.h: Add header guardsEdward O'Callaghan
Change-Id: I34c27bbce3ce958a33d547c727d9733d3b2d1670 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6400 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-07-28IOAPIC: Fix missing stdint includeKyösti Mälkki
Change-Id: Ib26f48d3ac66788246834cdc25d97910cd79fe98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6264 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-17misc,ASL: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I5060052e268c6a6303d77fdf4380a55ac2ad5ae2 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6296 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-08arch: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I472f3b70226ea5236ba6fc231f0f257f0f0eed9d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6206 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-03ACPI: Recover type of wakeup in acpi_is_wakeup()Kyösti Mälkki
Update acpi_slp_type early in ramstage. Change-Id: I30ec2680d28b880171217e896f48606f8691b099 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6142 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-29build: remove -ccopts mechanismPatrick Georgi
We now use the slightly more familiar CFLAGS_* and CPPFLAGS_* for the same purpose. Change-Id: Ifd2bd13f67f71fa0a15611a6d11a6a4c7994271b Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5875 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-06-29arch/x86/include/bootblock_common.h: Sanitize header inclusionEdward O'Callaghan
Sanitize the inclusion of mc146818rtc.h in bootblock_common.h Change-Id: I37d9ffd1375aedbf1f3eaa4ddce27e16166ce0b9 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6119 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-06-28armv7: We don't use CPPFLAGS anymorePatrick Georgi
CPPFLAGS is only used as qualified variant (like CPPFLAGS_armv7) now. Change-Id: If8b570ace4ac92d1fdb38ca3f7fef6c79d513a95 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5874 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2014-06-27build: Pass correct disassembly flags in Clang buildEdward O'Callaghan
On SVR4-derived platforms, the character `/' is treated as a comment character, which means that it cannot be used in expressions. The `--divide' option turns `/' into a normal character. This seems to be needed with our local build of binutils since we don't yet use the internal assembler/disassembler of the Clang tooling. Change-Id: I344fc8670fd5d994f3b63308a513dd367aefc7f9 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5813 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-26PIRQ tables: Fix typosKyösti Mälkki
Change-Id: I4d8abe3841378e06515e1b3a8f22d78425d08449 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6109 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-25Declare acpi_is_wakeup_early() only onceKyösti Mälkki
Change-Id: I5314d76168c40a6327d4a9ac3b4f4fb05497d6fc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4525 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-24MP Table: Change types to be consistent with the specMike Loptien
Update the elements in the MP Spec structures with appropriate types to more accurately reflect the real sizes of the bit fields in the MP Tables. Also add a function for PCI I/O interrupts since these are handled slightly differently than the other I/O interrupt entries. The src_bus_irq field is defined where Bits 1-0: PIRQ pin: INT_A# = 0, INT_B# = 1, INT_C# = 2, INT_D# = 3 Bits 2-6: Originating PCI Device Number Bit 7: Reserved Change-Id: I693407beaa0ee454f49464e43ed45d8cba3b18fc Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/6050 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-21Misc: Use acpi_is_wakeup_s3()Kyösti Mälkki
Change-Id: I46906e6d68775edc5cfe199cfeb465db4da2691f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6072 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-20ACPI: Add acpi_is_wakeup_s3()Kyösti Mälkki
Test explicitly for S3 resume. Also switch to use IS_ENABLED(). Change-Id: I17ea729f51f99ea8d6135f2c7a807623f1286238 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6070 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-20ACPI S3 support: Add acpi_s3_resume_allowed()Kyösti Mälkki
Add this to reduce the amount of preprocessor conditionals used in the source, compiler currently resolves this to a constant. Once we have gone through all #if CONFIG_HAVE_ACPI_RESUME cases, we may change the implementation to enable/disable S3 support runtime. Change-Id: I0e2d9f81e2ab87c2376a04fab38a7c951cac7a07 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6060 Tested-by: build bot (Jenkins)
2014-06-16MP Spec: Correct the Virtual Wire assignmentMike Loptien
Virtual Wire mode is set by writing 0 to the the MPTable Feature2 bit field 'IMCR'. The virtualwire variable was initially defined as writing a 1 to this bit field which would actually set PIC mode instead of Virtual Wire mode. However, nearly every mainboard called the MPTables with virtualwire = 0, which actually had the effect of setting Virtual Wire mode. I am correcting the definition but leaving the call to write the MPTables with virtualwire = 0, which is how most mainboards are already setting the tables up. See the MP Spec table 4-1 for more details: Bit 7: IMCRP. When the IMCR presence bit is set, the IMCR is present and PIC Mode is implemented; otherwise, Virtual Wire Mode is implemented. http://download.intel.com/design/archives/processors/pro/docs/24201606.pdf Change-Id: I039d88134aabd55166c2b68aa842bacbfcc0f42b Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/5977 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-16MP Spec: Add copyright headerMike Loptien
Adding the copyright header to the MP Spec files because they were not included before. Change-Id: Ifcd217a53bf8df19b28e251a7cac8b92be68d1fc Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/5981 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-06build: Drop libgcc runtime wrapper in Clang buildsEdward O'Callaghan
This GCC specific workaround of wrapping of libgcc runtime symbols with gcc.c is not nessary with libcompiler-rt linkage. Change-Id: I50a2bc99d97f68a2ad2b51a92ea0e7086bab35fe Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5812 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-01lenovo: Make version look like something thinkpad_acpi would acceptVladimir Serbinenko
thinkpad_acpi checks that BIOS version matches some pattern. Report version in this form. Not cleaned up as the idea of this patch seems to be met with resistance. Can make it Thinkpad-specific if the idea is accepted. Change-Id: I15e33e87e7a7f42d6a06f12fb39b5172153af8a1 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4650 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-01acpigen: Add acpigen_emit_eisaid.Vladimir Serbinenko
Change-Id: Ib92142a133445018cd152dabe299792ba5f36548 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5240 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-26console: Add console for GDBKyösti Mälkki
Connection of UARTs to GDB stub got lost in the console transition process, bring it back. In theory, GDB stub should work also over usbdebug, but that solution is not really tested at all yet. Change-Id: I90e05e8132889e788b92e055ee191f35add43bbc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5343 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-25acpigen: Add acpigen_write_irq.Vladimir Serbinenko
Change-Id: Iba52dc2d52b7ac9a65d1d17b43e7204f5ede373e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5241 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-22x86/include/arch/acpi.h: remove incorrect semicolonMartin Roth
The semicolon really shouldn't be in the include... Change-Id: I90a0f516857365fddd21311cd703132af8d51007 Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5808 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-19build: use CFLAGS_* in more places where they're neededPatrick Georgi
After moving out -m32 from CC_*, 64bit compilers need CFLAGS_* in more places to handle everything in 32bit as appropriate. Change-Id: I692a46836fc0ba29a3a9eb47b123e3712691b45d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5789 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-19build: move include paths where they belongPatrick Georgi
They're _not_ part of the compiler binary, so they have no place in $(CC_*) Change-Id: I1e1c3c0be6f75629450a824ea834e1614d48ed9b Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5785 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17build: break compiler flags out of $(CC)Patrick Georgi
Having more than the executable in $(CC) only leads to trouble in a number of situations. Change-Id: I7642ca4068b3a3bd5798219d74de9e0eb85bb4e5 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5769 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17build: separate CPPFLAGS from CFLAGSPatrick Georgi
There are a couple of places where CPPFLAGS are pasted into CFLAGS, eliminate them. Change-Id: Ic7f568cf87a7d9c5c52e2942032a867161036bd7 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5765 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17build: CPPFLAGS is more common than INCLUDESPatrick Georgi
Rename INCLUDES to CPPFLAGS since the latter is more commonly used for preprocessor options. Change-Id: I522bb01c44856d0eccf221fa43d2d644bdf01d69 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5764 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-11SeaBIOS: Fix cpp usePatrick Georgi
No need to pass CPP down to SeaBIOS, it's not architecture specific and they define their own variable. Change-Id: I811aaf3929fa11cc01b7f168ccd310008e21e60c Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5715 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10Arch-level Kconfig menu cleanupFurquan Shaikh
Remove arch-level Kconfig menu option as it shows all available architectures in make menuconfig. Instead pull the bootblock options for choice and update image to top-level Kconfig since it is already present for both x86 and arm. Change-Id: Iab9c4539f05cd54a7f751565fefcaf7b6f0edc86 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5673 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-06Introduce stage-specific architecture for corebootFurquan Shaikh
Make all three coreboot stages (bootblock, romstage and ramstage) aware of the architecture specific to that stage i.e. we will have CONFIG_ARCH variables for each of the three stages. This allows us to have an SOC with any combination of architectures and thus every stage can be made to run on a completely different architecture independent of others. Thus, bootblock can have an x86 arch whereas romstage and ramstage can have arm32 and arm64 arch respectively. These stage specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain and compiler flags for every stage. These options can be considered as either arch or modes eg: x86 running in different modes or ARM having different arch types (v4, v7, v8). We have got rid of the original CONFIG_ARCH option completely as every stage can have any architecture of its own. Thus, almost all the components of coreboot are identified as being part of one of the three stages (bootblock, romstage or ramstage). The components which cannot be classified as such e.g. smm, rmodules can have their own compiler toolset which is for now set to *_i386. Hence, all special classes are treated in a similar way and the compiler toolset is defined using create_class_compiler defined in Makefile. In order to meet these requirements, changes have been made to CC, LD, OBJCOPY and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others. Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the toolsets are defined using create_class_compiler. Few additional macros have been introduced to identify the class to be used at various points, e.g.: CC_$(class) derives the $(class) part from the name of the stage being compiled. We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER as they do not make any sense for coreboot as a whole. All these attributes are associated with each of the stages. Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5577 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-05-03Move redundant Makefile rules from arch to top level.Furquan Shaikh
Remove all the common Makefile rules like coreboot.pre, coreboot.pre1 and others from arch level Makefile.inc to top level Makefile.inc. Also, organize Makefile.inc at arch level into per-stage rules and variables. Change-Id: I7dc5b2d31c959b55bb92d9c7811427c4dada1db5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5571 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-02arch/x86/boot: Indent mpspec.c and make a loop more legibleEdward O'Callaghan
Fix some space->tab style and a for-for loop embedded to be more understandable/readable. Change-Id: I740c544e8c9330e6efbbd66a5c1e6a4a33d1a75e Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5631 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-30uart: Support multiple portsKyösti Mälkki
The port for console remains to be a compile time constant. The Kconfig option is changed to select an UART port with index to avoid putting map of UART base addresses in Kconfigs. With this change it is possible to have other than debug console on different UART port. Change-Id: Ie1845a946f8d3b2604ef5404edb31b2e811f3ccd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5342 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-26Rename coreboot_ram stage to ramstageFurquan Shaikh
Rename coreboot_ram stage to ramstage. This is done in order to provide consistency with other stage names (bootblock, romstage) and to allow any Makefile rule generalization, required for patches to be submitted later. Change-Id: Ib66e43b7e17b9c48b2d099670ba7e7d857673386 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5567 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-18build rules: Identify build stage with simple variablesKyösti Mälkki
Provide simple environment variables telling which stage of boot is being built. Also move this to arch-agnostic location. Change-Id: I8cbb5cf91f53e01c06e7d672b5be3f5c235f911d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5410 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2014-04-18console: Split ROMCC helpersKyösti Mälkki
These are potentially useful with GDB or SerialICE too. Also it reduces the amount of actual code we put in romcc_console. Change-Id: Id8c56e979660ad9f4eef39c648f68c7ec60edfba Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5339 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-18console: Use romstage code for ramstage and SMMKyösti Mälkki
Console is arch-agnostic and there is no need for separate implementations for romstage and ramstage. For SMM there is console only if DEBUG_SMI is selected. Change-Id: I7028eeeff8bfbb9c8552972436b29a7508834d87 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5338 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-18console: Drop driver list in ramstageKyösti Mälkki
This framework was only available in ramstage. So we had to define console output functions separately for bootblock, romstage and SMM. Follow-up patches will re-enable all the consoles removed here, in a more flexible fashion, and with less lines-of-code and copy-paste. Also the driver list is not in a well-defined order and some of the loops could exit without visiting all drivers. NOTE: This build has no console in ramstage. Change-Id: Iaddc495aaca37e2a6c2c3f802a0dba27bf227a3e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5337 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09console: Refactor uart8250/NE2KKyösti Mälkki
Do this for symmetry with romstage_console.c. Change-Id: If17acfc3da07b1dbefa87162c3c7168deb7b354a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5330 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09console: Move newline translation outside console_tx_byteKyösti Mälkki
This gives us completely transparent low-level function to transmit data. Change-Id: I706791ff43d80a36a7252a4da0e6f3af92520db7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5336 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09console: Hide global console_loglevelKyösti Mälkki
Change-Id: I7bdc468bc3f74516abb2c583bdb5b6d7555d987c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5333 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09console: Unify do_printk()Kyösti Mälkki
Change-Id: I6c50e47d9d2d0d1f42beee477e49b2a0054d1786 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5332 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09console: Split console_init()Kyösti Mälkki
Splitting the version prompt satisfies some requirements ROMCC sets for the order in which we include source files. Also GDB stub will need console hardware before entering main(). Change-Id: Ibb445a2f8cfb440d9dd69cade5f0ea41fb606f50 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5331 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09uart: Redefine Kconfig optionsKyösti Mälkki
Option DRIVERS_UART builds with support for UART hardware. Option CONSOLE_SERIAL enables the console output for UART. Those x86 boards that do not have serial port on SuperIO should select NO_UART_ON_SUPERIO to disable 8250 UART for the default configuration. Removes: CONSOLE_SERIAL_UART HAVE_UART_IO_MAPPED HAVE_UART_MEMORY_MAPPED Renames: CONSOLE_SERIAL8250 -> DRIVERS_UART_8250IO CONSOLE_SERIAL8250MEM -> DRIVERS_UART_8250MEM Change-Id: Id3afa05f85c0d6849746886db8b6c2ed6c846b61 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5311 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 06:23:52 +0000