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2014-09-09arm: Update a stale comment in bootblock .S filesDavid Hendricks
This just updates a comment which refers to "board_init_f". We use bootblock main() in coreboot. Change-Id: I4cb6b3c11f163b67fe48de495d13dce88710efc0 Reviewed-on: https://chromium-review.googlesource.com/172095 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 65139f29682cedca8dfb58b3dfe67eab64299064) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6791 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-09-09exynos: Install the BL1 and set the checksum in the Makefile.Gabe Black
Install the BL1 and set up the checksum in the Makefile instead of relying on post processing. Import the exynos checksum script, split it in two and simplify it significantly. Stop putting the CBFS header in the midst of the bootblock so that it can be checksummed before CBFS is put together. Stop saving space for it and leaving an anchor in the bootblock which nobody looks for. Change-Id: Icbb5a5914ece60b2827433b6dc29d80db996ea6c Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/179229 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit aa3a416705517c0a6ddfdeb19905ac8cafb33df1) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6834 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-09ARMv4: Add a minimal version of cpu.h.Gabe Black
All this version does is define asmlinkage to be nothing. It's required by the threading header file which is brought in by the timer implementation which I think is the hook for thread switching. Change-Id: Id57261d7c2c5ff8be00b0ad71bf7aaa9f3e24c1d Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171801 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit e00379f54802066fd3e0685b291cdec289078055) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6831 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-09-09ARM: Add an ARMv4 architecture version.Gabe Black
This is needed for the tegra124's bootblock and includes enough implementation to support that use. No caching is supported, although there are function prototypes and stub implementations to satisfy includes and linking. Change-Id: Ib79dde8c30eda98b3e823cba2ff6115a610bb2e8 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171401 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 221dc76b3ce4c1d73851c432333e091e1c60f0cb) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6783 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-09-08ARM: Generalize armv7 as arm.Gabe Black
There are ARM systems which are essentially heterogeneous multicores where some cores implement a different ARM architecture version than other cores. A specific example is the tegra124 which boots on an ARMv4 coprocessor while most code, including most of the firmware, runs on the main ARMv7 core. To support SOCs like this, the plan is to generalize the ARM architecture so that all versions are available, and an SOC/CPU can then select what architecture variant should be used for each component of the firmware; bootblock, romstage, and ramstage. Old-Change-Id: I22e048c3bc72bd56371e14200942e436c1e312c2 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171338 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 8423a41529da0ff67fb9873be1e2beb30b09ae2d) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> ARM: Split out ARMv7 code and make it possible to have other arch versions. We don't always want to use ARMv7 code when building for ARM, so we should separate out the ARMv7 code so it can be excluded, and also make it possible to include code for some other version of the architecture instead, all per build component for cases where we need more than one architecture version at a time. The tegra124 bootblock will ultimately need to be ARMv4, but until we have some ARMv4 code to switch over to we can leave it set to ARMv7. Old-Change-Id: Ia982c91057fac9c252397b7c866224f103761cc7 Reviewed-on: https://chromium-review.googlesource.com/171400 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 799514e6060aa97acdcf081b5c48f965be134483) Squashed two related patches for splitting ARM support into general ARM support and ARMv7 specific pieces. Change-Id: Ic6511507953a2223c87c55f90252c4a4e1dd6010 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6782 Tested-by: build bot (Jenkins)
2014-09-05Implement ACPI in a per device wayVladimir Serbinenko
This approach avoids having same basic tables 150-lines mantra over 100 times in codebase. Change-Id: I76fb2fbcb9ca0654f2e5fd5d90bd62392165777c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6801 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-09-02acpigen: Correctly handle root scopeVladimir Serbinenko
Change-Id: I9b3c9109b01e348259e64e93a4397212216ab152 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6799 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-09-02smbios.c: Fix mismerge which led to laptop being default typeVladimir Serbinenko
Change-Id: I97ccd08a5e7f094908ed3a85ddae53b158124995 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6823 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-30smbios: reorganise OEM strings handling.Vladimir Serbinenko
OEM strings should not be handled by mobo code but by common code with strings collected from all devices. Change-Id: Ibde61a1ca79845670bc0df87dc6c67fa868d48a9 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6788 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-08-29smbios: Define and use enclosure types.Vladimir Serbinenko
Change-Id: Ib5b92120cbe2ca41c9813e8caeb03161f4d3954c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6786 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-08-29arm: libpayload: Make cache invalidation take pointers instead of integersJulius Werner
This minor refactoring patch changes the signature of all limited cache invalidation functions in coreboot and libpayload from unsigned long to void * for the address argument, since that's really what you have in 95% of the cases and I think it's ugly to have casting boilerplate all over the place. Change-Id: Ic9d3b2ea70b6aa8aea6647adae43ee2183b4e065 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167338 (cherry picked from commit d550bec944736dfa29fcf109e30f17a94af03576) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6623 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-28ARM: Make it possible to use a custom bootblock implementation.Gabe Black
Tegra needs to use a custom bootblock implementation because it starts on a coprocessor which uses ARMv4. It doesn't have the same control registers, caches, etc., and the regular bootblock gets exceptions and dies. Change-Id: Id197db2939bc840ad64244d6e2017fc5c89e0cbd Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171018 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit a66393fdd6fe68757e394b8a611e610f1938771d) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6710 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2014-08-22ARM: Overhaul the ARM Makefile.Gabe Black
The ARM Makefile was copied from x86 and then modified, and as a result it was carrying a lot of baggage. On top of that, the extra complication made it inflexible, and we need a lot of flexiblity in order to support the fact that the Tegra124 starts on an ARMv4 coprocessor instead of one of the ARMv7 main CPUs. Change-Id: Ia6ddc27619bdb51e152ad0c628ad6f3037c103ce Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171017 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 512d942788336c8d52470135b43ee4e6a1c95f6c) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6709 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-14armv7: mark EABI compatibility symbols as usedStefan Reinauer
These symbols are not used anywhere in our C code, so when using GCC's link time optimization feature they will be dropped even though they're needed by libgcc. Hence we need to mark them as used so GCC does not stumble and fall over its own guts. Change-Id: Ib2e9ea2610b57ab8244d5b699dd56025a4f08a01 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/168773 (cherry picked from commit 416ffc880bcf4122b5430fbd9d9547c83886af2f) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6640 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-14ARMv7/Exynos: Fix memory location assumptionsStefan Reinauer
This patch cleans out a lot of unused variables in the ARM Kconfig files and introduces CONFIG_RAMSTAGE_BASE which is similar to CONFIG_RAMBASE on x86. This gets rid of the hard coded assumption that on ARM coreboot is always executed at the lowest DRAM address. But in fact, this might not be true because we might want coreboot to live at the end of RAM, or in SRAM Change-Id: I03e992645f9eb730e39a521aa21f702959311f74 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/168645 Reviewed-by: David Hendrix <dhendrix@chromium.org> Tested-by: David Hendrix <dhendrix@chromium.org> (cherry picked from commit 15b87892eb2d5e27759c49dc6c8c7e626f651d77) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6634 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-13ARMv7: drop dead code from Makefile.incStefan Reinauer
This commented out code is a left over from x86. Change-Id: Ice806000c73d5a068962914d067d4de7b3d75f45 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/168961 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: David Hendrix <dhendrix@chromium.org> (cherry picked from commit 9d700cf35d2283a088e704c0ebd34e6f58f54993) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6639 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-12armv7/Makefile.inc, cpu/Makefile.inc: align output of printfDaniele Forsi
Fix whitespace. Change-Id: I9e28b819d685851a84cee6c5a71458e07d0ec808 Signed-off-by: Daniele Forsi <dforsi@gmail.com> Reviewed-on: http://review.coreboot.org/6577 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-11coreboot classes: Add dynamic classes to corebootFurquan Shaikh
Provide functionality to create dynamic classes based on program name and architecture for which the program needs to be compiled/linked. define_class takes program_name and arch as its arguments and adds the program_name to classes-y to create dynamic class. Also, compiler toolset is created for the specified arch. All the files for this program can then be added to program_name-y += .. Ensure that define_class is called before any files are added to the class. Check subdirs-y for order of directory inclusion. One such example of dynamic class is rmodules. Multiple rmodules can be used which need to be compiled for different architectures. With dynamic classes, this is possible. Change-Id: Ie143ed6f79ced5f58c200394cff89b006bc9b342 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/6426 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-10armv7: Support stack dump after exceptionsJulius Werner
This patch enhances the armv7 exception handlers in Coreboot and libpayload to show the correct SP and LR registers from the aborted context, and also dump a part of the current stack. Since we cannot access the banked registers of SVC mode from a different exception mode, it changes Coreboot (and its payloads) to run in System mode instead. As both modes can execute all privileged instructions, this should not have any noticeable effect on firmware operation (please correct me if I'm wrong!). Change-Id: I0e04f47619e55308f7da4a3a99c9cae6ae35cc30 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170045 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit d0db2f5e938200e3f5899c5e1f1606ab2dd5b334) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6538 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-10ARM: Eliminate the unused interrupts.c.Gabe Black
This file isn't compiled into anything, and probably wouldn't since it has a lot of baggage from it's U-Boot origins. Change-Id: I29d87afd2a283010a653d3d48fdd3a79622e3b99 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/170423 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: David Hendrix <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 1146c570f0e448f7db4ec82749e91099c946a2dc) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6544 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2014-08-08ARMv7: Add stdint types needed for vboot libraryStefan Reinauer
Change-Id: I778ea787b20a7d7d7b202b1b5e7f956d2fde6629 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/169621 (cherry picked from commit 499a4802b5ad070a0b82f3b291073aa05fa7946e) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6523 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-08ARMV7: threading support for cooperative multitaskingRonald G. Minnich
These functions add support for cooperative multitasking. Currently, since we only have one ARM SOC that uses or supports multitasking, arch_get_thread_stackbase returns CONFIG_STACK_BOTTOM for the thread stack. We may end up having to make a cpu-specific function that arch_get_thread_stackbase calls, but let's avoid adding complexity until we're sure we need to. We also wish to avoid creating Yet Another Config Variable but will do so if pressed. The switch code only saves r4-r11 and lr, which is consistent with the standard. Change-Id: I0338a9c11127351e1f3a190bc51a7a558420b141 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66845 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit 22b62af3c26b6b504498b434d29a56a8932f3061) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6517 Tested-by: build bot (Jenkins)
2014-08-07armv7: Fix dcache writethrough policy handlingDavid Hendricks
The "bufferable" bit was erroneously set for the writethrough policy making it the same as writeback. (credit to jwerner for pointing this out) Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I567d57f0e522cb4b82988894ba9b4638642bf8db Reviewed-on: https://chromium-review.googlesource.com/167323 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Tested-by: ron minnich <rminnich@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 36cf13839604c349692865475f3011afd08965b4) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6515 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-07Possible thread stack implementation.Ronald G. Minnich
Architecture provides a function for thread stack base, thread code uses it. Build and boot tested on Falco with multitasking on and off. Change-Id: I5016fab47f9954379acf7702ac7965b0a70c88ed Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66578 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit 3c6afef30c1a0ad6fba0fb76acc792184d924247) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6513 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-07exynos: Set up caching in the bootblock.Gabe Black
This improves firmware boot time substantially. Because cbmem isn't available yet, we need to allocate some space in sram for the ttb. Doing cache initialization in the bootblock means we can implement this once per CPU instead of once per mainboard. Old-Change-Id: Iad339de24df8ec2e23f91fe7bf57744e4cc766c5 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65938 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit c32b9b32ad933e627b9ea98434b392239b1fea73) exynos5420: flush caches and disable MMU in resume path This patch flushes the caches and disables the MMU before resuming. c32b9b3 ("Set up caching in the bootblock.") had a bug where the dcache and MMU remained enabled in the resume path. This caused the machine to hang on resume. However, other bugs were preventing us from testing this properly earlier on so it went unnoticed until now. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: Ib1774f09d286a4d659da9fc2dad1d7a6fc1ebe5e Reviewed-on: https://chromium-review.googlesource.com/67007 Reviewed-by: ron minnich <rminnich@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 4fdf9763d25f70fd1e3591f6ff9785f78dd6170d) Squashed two related commits. Change-Id: Ibd42b28bb06930159248130e5ceaddb3b4b6cc2a Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6511 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-06Set armv7 up for cpu_info to work as on x86 (so threads can work)Ronald G. Minnich
On x86, cpu_info lives at the top of stack. Make the arm do that as well, as the threading model needs that and so will multicore support. As part of this change, make the stack size a power of 2. Also make it much smaller -- 2048 bytes is PLENTY for ram stage. Note that the small stack size is counterintuitive for rom stage. How can this work in rom stage, which needs a HUGE stack for lzma? The main use of STACK_SIZE has always been in ram stage; since 2002 or so it was to size per-core stacks (see, e.g., src/arch/x86/lib/c_start.S:.space CONFIG_MAX_CPUS*CONFIG_STACK_SIZE and, more recently, thread stacks. So, we define the STACK_TOP for rom and ram stage, but the STACK_SIZE has no real effect on the ROM stage (no hardware red zones on the stack) and hence we're ok with actually defining the "wrong" stack size. In fact, the coreboot_ram ldscript for armv7 sizes the stack by subtracting CONFIG_STACK_BOTTOM from CONFIG_STACK_TOP, so we replicate that arithmetic in bootblock.inc Observed stack usage in ramstage: BS: BS_PAYLOAD_LOAD times (us): entry 1 run 153887 exit 1 Jumping to boot code at 23104044 CPU0: stack: 02072800 - 02073000, lowest used address 020728d4, stack used: 1836 bytes entry = 23104044 Which means we do need 2K, not 1K. Change-Id: I1a21db87081597efe463095bfd33c89eba1d569f Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66135 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit f011097e9f2bfb2f4c1109d465be89a79a65ba3e) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6501 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-03arch/x86/Makefile.inc: trivial: fix indent of informative output about bootblockDaniele Forsi
Fixes the 4th line of this sequence: ROMCC generated/bootblock.inc GEN generated/bootblock_inc.S CC generated/bootblock.s CC generated/bootblock.o GEN generated/bootblock.ld Change-Id: Ic0704b83ec9c4191e26a94e0d69cbf4c0486ceed Signed-off-by: Daniele Forsi <dforsi@gmail.com> Reviewed-on: http://review.coreboot.org/6466 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-01armv7: add wrapper for DCCSW (data cache clean by set/way)David Hendricks
This adds a wrapper for data cache clean (without invalidate) by set/way. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I09ee1563890350a6c1d04f1b96ac5d0c042e2af2 Reviewed-on: https://gerrit.chromium.org/gerrit/66118 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit 05bc4f8564c547eacb9cc840a03b916b3c1c6001) armv7: clean but do not invalidate caches between stages This cleans the caches without invalidating them between stages. The dcache content should still be valid when the next stage begins, so we should see a small performance gain. (thanks to gabeblack for pointing this out) Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: Ie18d163f3a78e2786e9fbc7479c8bd896b8ac3aa Reviewed-on: https://gerrit.chromium.org/gerrit/66119 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit 619bfe4cf9b93847e38d03d7076beb78fbfa1d1d) armv7: Make coreboot and libpayload cache files the same This merges the difference between the ARM version of cache.c and cache.h for libpayload and coreboot. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I246d2ec98385100304266f4bb15337a8fcf8df93 Reviewed-on: https://gerrit.chromium.org/gerrit/66120 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit 0c92f694034f1e94a8aa7811251738c9dc3db2c6) ARM: Fix cache cleaning operation. There was no behavior defined for OP_DCCSW in dcache_op_set_way, so it silently did nothing. Since we started using that to clean the cache between stages and I have a change that enables caches earlier on, this was preventing booting on pit. Old-Change-Id: I3615b6569bf8de195d19d26b62f02932322b7601 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66234 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 99241468cb9dcc86fcca9266ffe72baa88a1f79f) libpayload: Fix data cache cleaning on ARM. A similar fix was made to coreboot where OP_DCCSW was silently not doing anything in dcache_op_set_way. Old-Change-Id: Ia0798aef0cd02da7d1a14b7affa05038a002ab3b Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66236 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 6f6596a182a6780a2e997ac320733722697990c5) Squashed five related commits. Change-Id: I763d42bd5dd9f58734e1e21eb7c8ce3ce2ea56ee Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6418 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-31payloads/external/SeaBIOS: Use coreboot’s serial console settingsMartin Roth
Set up the serial console on SeaBIOS to match coreboot's settings. Previously, we were just forcing it on, and setting it to 0x3f8. Change-Id: I107245c8bd1ba2cf948c6671337c6169226aaaaf Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6363 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-31armv7/exynos5420: Configure CPU cores for kernel to enable SMP.Hung-Te Lin
The SMP on Exynos 5420 requires setting a special page and entry wrappers in firmware side (SRAM) so kernel can start cores (and to switch clusters). Change-Id: I77ca98bb6cff5b13e95dd29228e4536302f0aee9 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/64770 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit 4a11c7ab78cc0811df0f88763b0af8b9f24e5433) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6405 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-30arch/x86/include/arch/interrupt.h: Add header guardsEdward O'Callaghan
Change-Id: I34c27bbce3ce958a33d547c727d9733d3b2d1670 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6400 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-07-28IOAPIC: Fix missing stdint includeKyösti Mälkki
Change-Id: Ib26f48d3ac66788246834cdc25d97910cd79fe98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6264 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-17misc,ASL: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I5060052e268c6a6303d77fdf4380a55ac2ad5ae2 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6296 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-08arch: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I472f3b70226ea5236ba6fc231f0f257f0f0eed9d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6206 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-03ACPI: Recover type of wakeup in acpi_is_wakeup()Kyösti Mälkki
Update acpi_slp_type early in ramstage. Change-Id: I30ec2680d28b880171217e896f48606f8691b099 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6142 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-29build: remove -ccopts mechanismPatrick Georgi
We now use the slightly more familiar CFLAGS_* and CPPFLAGS_* for the same purpose. Change-Id: Ifd2bd13f67f71fa0a15611a6d11a6a4c7994271b Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5875 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-06-29arch/x86/include/bootblock_common.h: Sanitize header inclusionEdward O'Callaghan
Sanitize the inclusion of mc146818rtc.h in bootblock_common.h Change-Id: I37d9ffd1375aedbf1f3eaa4ddce27e16166ce0b9 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6119 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-06-28armv7: We don't use CPPFLAGS anymorePatrick Georgi
CPPFLAGS is only used as qualified variant (like CPPFLAGS_armv7) now. Change-Id: If8b570ace4ac92d1fdb38ca3f7fef6c79d513a95 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5874 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2014-06-27build: Pass correct disassembly flags in Clang buildEdward O'Callaghan
On SVR4-derived platforms, the character `/' is treated as a comment character, which means that it cannot be used in expressions. The `--divide' option turns `/' into a normal character. This seems to be needed with our local build of binutils since we don't yet use the internal assembler/disassembler of the Clang tooling. Change-Id: I344fc8670fd5d994f3b63308a513dd367aefc7f9 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5813 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-26PIRQ tables: Fix typosKyösti Mälkki
Change-Id: I4d8abe3841378e06515e1b3a8f22d78425d08449 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6109 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-25Declare acpi_is_wakeup_early() only onceKyösti Mälkki
Change-Id: I5314d76168c40a6327d4a9ac3b4f4fb05497d6fc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4525 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-24MP Table: Change types to be consistent with the specMike Loptien
Update the elements in the MP Spec structures with appropriate types to more accurately reflect the real sizes of the bit fields in the MP Tables. Also add a function for PCI I/O interrupts since these are handled slightly differently than the other I/O interrupt entries. The src_bus_irq field is defined where Bits 1-0: PIRQ pin: INT_A# = 0, INT_B# = 1, INT_C# = 2, INT_D# = 3 Bits 2-6: Originating PCI Device Number Bit 7: Reserved Change-Id: I693407beaa0ee454f49464e43ed45d8cba3b18fc Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/6050 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-21Misc: Use acpi_is_wakeup_s3()Kyösti Mälkki
Change-Id: I46906e6d68775edc5cfe199cfeb465db4da2691f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6072 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-20ACPI: Add acpi_is_wakeup_s3()Kyösti Mälkki
Test explicitly for S3 resume. Also switch to use IS_ENABLED(). Change-Id: I17ea729f51f99ea8d6135f2c7a807623f1286238 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6070 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-20ACPI S3 support: Add acpi_s3_resume_allowed()Kyösti Mälkki
Add this to reduce the amount of preprocessor conditionals used in the source, compiler currently resolves this to a constant. Once we have gone through all #if CONFIG_HAVE_ACPI_RESUME cases, we may change the implementation to enable/disable S3 support runtime. Change-Id: I0e2d9f81e2ab87c2376a04fab38a7c951cac7a07 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6060 Tested-by: build bot (Jenkins)
2014-06-16MP Spec: Correct the Virtual Wire assignmentMike Loptien
Virtual Wire mode is set by writing 0 to the the MPTable Feature2 bit field 'IMCR'. The virtualwire variable was initially defined as writing a 1 to this bit field which would actually set PIC mode instead of Virtual Wire mode. However, nearly every mainboard called the MPTables with virtualwire = 0, which actually had the effect of setting Virtual Wire mode. I am correcting the definition but leaving the call to write the MPTables with virtualwire = 0, which is how most mainboards are already setting the tables up. See the MP Spec table 4-1 for more details: Bit 7: IMCRP. When the IMCR presence bit is set, the IMCR is present and PIC Mode is implemented; otherwise, Virtual Wire Mode is implemented. http://download.intel.com/design/archives/processors/pro/docs/24201606.pdf Change-Id: I039d88134aabd55166c2b68aa842bacbfcc0f42b Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/5977 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-16MP Spec: Add copyright headerMike Loptien
Adding the copyright header to the MP Spec files because they were not included before. Change-Id: Ifcd217a53bf8df19b28e251a7cac8b92be68d1fc Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/5981 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-06build: Drop libgcc runtime wrapper in Clang buildsEdward O'Callaghan
This GCC specific workaround of wrapping of libgcc runtime symbols with gcc.c is not nessary with libcompiler-rt linkage. Change-Id: I50a2bc99d97f68a2ad2b51a92ea0e7086bab35fe Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5812 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-01lenovo: Make version look like something thinkpad_acpi would acceptVladimir Serbinenko
thinkpad_acpi checks that BIOS version matches some pattern. Report version in this form. Not cleaned up as the idea of this patch seems to be met with resistance. Can make it Thinkpad-specific if the idea is accepted. Change-Id: I15e33e87e7a7f42d6a06f12fb39b5172153af8a1 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4650 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-01acpigen: Add acpigen_emit_eisaid.Vladimir Serbinenko
Change-Id: Ib92142a133445018cd152dabe299792ba5f36548 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5240 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-12 17:14:19 +0000