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2015-03-29arch/x86/boot/smbios: Rename fill_dimm_manufacturer and make publicTimothy Pearson
Change-Id: Ib85701965337bb6231d8df59d43789dfe8a036d3 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9136 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-29arch/x86/boot/smbios: Add additional SMBIOS defines and enumsTimothy Pearson
Change-Id: I337584d1f4ce32094c24478a99418e0775cf9ab5 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9135 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-28armv8/secmon: SECMON_SRC is really SECMON_BINPatrick Georgi
It points to a binary. This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: I164d7f717a9523d187e2c215083e176b59fd5acc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 Reviewed-on: http://review.coreboot.org/9113 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arch/x86: Guard option table specific rules with HAVE_OPTION_TABLEPatrick Georgi
This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: Ia22c9fcbf8c629d0eb3f1356f80c4565f117d8b8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 Reviewed-on: http://review.coreboot.org/9110 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28build system: normalize linker script file namesPatrick Georgi
We have .lb, .lds, and .ld in the tree. Go for .ld everywhere. This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: I3126af608afe4937ec4551a78df5a7824e09b04b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 Reviewed-on: http://review.coreboot.org/9107 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-28arch/arm64: Drop extra commentPatrick Georgi
This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: I362e2f6a978de23e72e6fc9c83bc99457cd76d9c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 Reviewed-on: http://review.coreboot.org/9112 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arch/arm: drop extra commentPatrick Georgi
This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: I8a5dc66d8c0dc4ccdb6dc3d66b8cdbf50dc976ca Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 Reviewed-on: http://review.coreboot.org/9111 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28mips: fix API expectations that break buildsAaron Durbin
Add the approrpiate car* empty implementations as well as types included within the rest of coreboot to start building correctly. Change-Id: Ifaf10281f9a9e28f518f4694630cbffa3f8d187d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9150 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: Aaron Durbin <adurbin@google.com>
2015-03-28arm64: remove EL and mode from secmon_paramsAaron Durbin
Since PSCI dynamically determines which EL to transition to based on SCR_EL3 there's no need to provide that information. BUG=chrome-os-partner:30785 BRANCH=None TEST=Built and booted into kernel with MP. Change-Id: Ia59bc8116ec4ae9bde2e6cad1861f76c14f7d495 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8bc5f7c8a114568ede98478c2fbea2f8b7d97f0c Original-Change-Id: I8783b6315dca01464e14c9d2b20d009cf0beeb67 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218924 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9098 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: add psci support to secmonAaron Durbin
The PSCI functionality initially includes CPU_ON and CPU_OFF functions. Upon entering secmon if the parameters are non-NULL then a PSCI CPU_ON action is done for the current CPU. BUG=chrome-os-partner:32112 BRANCH=None TEST=Booted kernel with PSCI support. Brought up all CPUs in kernel using PSCI. Turned CPUs on and off. Change-Id: I256fa45a1c9889ff9d7990eb1898df1ec241c117 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 689ba03e313e7e52e9b74aa774897b55cbd52748 Original-Change-Id: I943826b7dbcc8e3f6c8c4b66344af8fac12ba94e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218923 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9097 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-03-28arm64: Provide secmon trampoline for restartAaron Durbin
If an exception is taken that the secmon won't return to, there needs to be way to reset that cpu's state w.r.t. stack usage. Therefore, provide secmon_trampoline which will reinitialize the exception stack and SP_EL0 and start executing with SP_EL0 like the initial state of the secmon entry. BUG=chrome-os-partner:30785 BRANCH=None TEST=Built and booted to kernel. Also tested when PSCI is employed in the kernel. Change-Id: Ie9f5bbe715dcbcf8b67ea40f9a3a5088ac7aa2ad Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f1f546ee3e9eca93baaa1ae0437351205bf548a5 Original-Change-Id: Ia3da75e1fa0251c8ea30eb0b0523c8a51c03b917 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218922 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9096 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-03-28arm64: fix smc bugs in secmonAaron Durbin
Two things: 1. Not returning once setting the return state. 2. mempcy(x, y, ARRAY_SIZE(x)) is not memcpy(x, y, sizeof(x)) With these 2 changes arguments and results are being processed correctly. BUG=chrome-os-partner:32112 BRANCH=None TEST=Built and brought up SMP using PSCI. Change-Id: If76a207e1a434a4c08faaa535f069d7386481e9e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 42d540afd4e6ea2b34cf3632ad2c683fcaa063c8 Original-Change-Id: I656b9c11e3bc07cc1664789a600eb88afd639f93 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218847 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9094 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: add smc layer to secmonAaron Durbin
In order to process PSCI commands SMC instructions need to be serviced. Provide a simple way for users of SMC to register their handlers by function. The SMC layer hooks into the exception processing, however it only processes AARCH64 SMC calls. All others are ignored. BUG=chrome-os-partner:32112 BRANCH=None TEST=Added nop smc call to depthcharge. SMC handled and continue booting to kernel. Change-Id: I378f13c29220ff9f37040f094bf9cfb69259af0c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 76d2febc50397348b68d38532b8f37e2b3cf6a30 Original-Change-Id: Ieaa29fa883b9f9d55fc62ba92a1d45452296efa4 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218846 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9092 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: initialize secmon environmentAaron Durbin
The exception vectors were not reinitialized in secmon yet. Add that as well as the split BSP vs non-BSP path. In doing so bring in the cpu.c semantics for determining bsp at runtime. BUG=chrome-os-partner:30785 BRANCH=None TEST=Built and booted to kernel. Also noted only one CPU printing messages. Change-Id: I26a7f9446f4422d2203b1d520e69f8dee9450b59 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 67f79c61c902ee614f029047255b4be35112cd32 Original-Change-Id: Ide66f13c24f5798d5983c481ce616ae2800d558c Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218845 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9091 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: provide entry points for BSP and non-BSPAaron Durbin
It's helpful to differentiate the startup paths for the BSP and the non-BSP. Therefore have c_entry be an 2 element array of function pointers. The non-BSP paths have an entry point one instruction after stage/module entry. BUG=chrome-os-partner:30785 BRANCH=None TEST=Built and booted to kernel. Change-Id: I40bb40462906f1b1eaf2db8584985095e8ac0bae Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ce10f954041b3fd581ad8a3d82dee567b68637fe Original-Change-Id: Ia573b1095dca5f69e371bf1ddf6b6df72fa3b52e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218844 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9090 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: split cpu.cAaron Durbin
The cpu.c contains some helpful construts as well as ramstage devicetree handling. Split the 2 pieces so that cpu.c can be reused in secmon. BUG=chrome-os-partner:30785 BRANCH=None TEST=Built and booted. Change-Id: Iec0f8462411897a255f7aa289191ce6761e08bb0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4f30f1186950424b65df6858965a09ca51637e4f Original-Change-Id: Ie87bd35bf1ccd777331250dcdaae07dab82d3d18 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218842 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9089 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: exception handler registrationAaron Durbin
In order to build upon the arm64 exception handlers need to be registered. This provides very basic support to register a handler for a specific exception vector. BUG=chrome-os-partner:30785 BRANCH=None TEST=Built and booted into kernel. Change-Id: If046f0736765a2efeb23201c1d2d1f7f7db47dd2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a82e5e8d5900ebef16abdb68701be6beeb9ca13a Original-Change-Id: I0f68a48101ff48d582f5422871b9e7e5164357e4 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218650 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9088 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: add spin table supportAaron Durbin
There was a hacky and one-off spin table support in tegra132. Make this support generic for all arm64 chips. BUG=chrome-os-partner:32082 BRANCH=None TEST=Ran with and without secure monitor booting smp into the kernel. Change-Id: I3425ab0c30983d4c74d0aa465dda38bb2c91c83b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 024dc3f3e5262433a56ed14934db837b5feb1748 Original-Change-Id: If12083a9afc3b2be663d36cfeed10f9b74bae3c8 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218654 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9084 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: add cpu_is_bsp() conceptAaron Durbin
It's helpful to know if the current running CPU is the BSP. Therefore, provide that semantic. BUG=chrome-os-partner:32082 BRANCH=None TEST=Built and booted to kernel. Change-Id: I18cb8ab5149c3337e22b1f6046b1af266be7e47c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b390dc70b658c207cd3b64408713ec4cddab3172 Original-Change-Id: I3d5518d1f6d6a78b14f25bb7ef79727605064561 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218653 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9083 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: provide run on all cpu but self semanticsAaron Durbin
In order to provide richer semantics for running code on all CPUs add an all-but-self construct. BUG=chrome-os-partner:32082 BRANCH=None TEST=Built and booted to kernel. Change-Id: If8dd28ff7f34d93592ab2025a65a2fd665e4e608 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9a4622f63a065f620f0c92ef92eeb2aa5c2b441d Original-Change-Id: Id18dc0423bcb0016ed36ace659b3f858e824c46c Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218652 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9082 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: Add support for secure monitorFurquan Shaikh
Secure monitor runs at EL3 and is responsible for jumping to the payload at specified EL and also to manage features like PSCI. Adding basic implementation of secure monitor as a rmodule. Currently, it just jumps to the the payload at current EL. Support for switching el and PSCI will be added as separate patches. CQ-DEPEND=CL:218300 BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles succesfully and secure monitor loads and runs payload on ryu Change-Id: If0f22299a9bad4e93311154e5546f5bae3f3395c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5e40a21115aeac1cc3c73922bdc3e42d4cdb7d34 Original-Change-Id: I86d5e93583afac141ff61475bd05c8c82d17d926 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214371 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9080 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: Adapt stage_entry to make it usable by secmonFurquan Shaikh
stage_entry is the best place to enter for secmon, since it sets up all the stacks right. The only need we need to take care is losing out on the parameter passed to secmon. This patch adds an entry point for secmon rmodule and moves the argument from x0 to x25, which is restored just before the jump to c_entry BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully Change-Id: I9638e9716b3bd5bff272e88fe9d965528d71e394 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ffedb03208bafab6d5886db0259ec205dd20588f Original-Change-Id: I74a7a609fbc08692d68708abe132cd219c89b456 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217570 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9079 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: initialize SCR_EL3 on all CPUsAaron Durbin
Provide SCR_EL3 initialization on all CPUs. This settings were chosen in such a way that nothing would need to be done if EL3 is abandoned after transitioning to EL2 or EL1. If persistent EL3 program is used those SCR policies can be updated within that program. BUG=chrome-os-partner:31634 BRANCH=None TEST=Built and booted through kernel. Printed out SCR setting for each CPU. Change-Id: Ib44acd8ae40dbca590740340632f5b72998e9dd8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f77b903afbafad7d439ec50fc48f1eaa37827d90 Original-Change-Id: Id659f0a98360fe8bbc80e5a623eba1526e81b400 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218300 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9078 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: initialize GIC for each CPUAaron Durbin
For every CPU that comes online initialize the GIC for that CPU. This allows the per-cpu register state to be initialized for every CPU that comes online. BUG=chrome-os-partner:31945 BRANCH=None TEST=Built and booted to kernel on ryu. Change-Id: I467ca38d51ac67ffc19b1b4fc6fafa9394a876c9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b2faf33fad80fd7ecb884d3ad40917f5a629a5b2 Original-Change-Id: I58d0ffcfe65cffc6a4dd2678c041219e1e698aaf Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217513 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9076 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-03-28arm64: Switch to EL2 for libpayload jumpFurquan Shaikh
CQ-DEPEND=CL:216826,CL:218300 BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully and we are able to start execution of libpayload in EL2 and reach kernel login prompt Change-Id: I233f9867470a4723f320dc0dcaa670a56dcf0f5d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 169948a2afeeb7848daeb37600963bd503527f1a Original-Change-Id: I336d73085f08ca03e533555a10b88f20d74b4347 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217826 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9074 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: Make exceptions use the transition libraryFurquan Shaikh
Transition library acts as a common interface for handling exceptions. The only thing that needs to be implemented by exception.c is the exc_dispatch routine to handle the exceptions as required. BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully and exceptions are tested using test_exc Change-Id: I90b4861909189adfe8449b9d4590965e6b743c00 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b83c9404407dd4dd2dda4e4eaed0b443f0f58425 Original-Change-Id: Ibb643d7ea2f9aabbc66439549ea2168fd66ced5e Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217143 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9071 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: Add support for transition libraryFurquan Shaikh
Transition library provides the following functionalities: 1) Setup the environment for switching to any particular EL and jump to the loaded program at that EL. In short "Execute program X at exception level Y using the state Z" 2) Provides routines for exception entry and exception exit that can be used by any program to implement exception handling. The only routine required by the program would be exc_dispatch which handles the exception in its own required way and returns by making a call to exc_exit. On exc_exit, the transition library unwinds the whole stack by popping out the saved state of xregs BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully and exceptions are tested for ramstage on ryu Change-Id: I8116556109665e61a53e4b3987d649e3cfed64a1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8ab888e8cae0c5f1e79b0e16ca292869f16f1cca Original-Change-Id: I90f664ac657258724dc0c79bd9f6ceef70064f90 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216375 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9070 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: Add useful macro definitions for register bitsFurquan Shaikh
BUG=chrome-os-partner:30785 BRANCH=None TEST=Coreboot compiles successfully Change-Id: I1fba44974314effa1065e3637aaa5430584a4cc6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a4791232de764ebe40d9b3de5c63479dec7da003 Original-Change-Id: I95fdff5d1580faf4cb4f85d6acae7a834b8ff0bf Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/218031 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9069 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: Reinit free_idx to 1 in mmu_initFurquan Shaikh
If mmu_init is called more than once then, free_idx should be reset to 1. Here, the assumption would be that mmu_init will not be called more than once. However, this is not necessarily true. Thus, free_idx should be reset to 1 every time we are initializing ttb from scratch. BUG=None BRANCH=None TEST=Compiles sucessfully and boots to kernel Change-Id: I5ac0af43346a492583380b0f15101390fc98d182 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 398a68c3b08d82cfa521d235af2c1922629bdf56 Original-Change-Id: Idb7424df7dd577f263f12d1527dbd7fb89216d40 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216906 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9068 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: check for NULL bus on DEVICE_PATH_CPU_CLUSTER devicesAaron Durbin
If there are no devices underneath a device in a devicetree the bus pointer in a struct device is NULL. Check for this condition before proceeding in walking through the children devices. BUG=chrome-os-partner:31761 BRANCH=None TEST=Ran through coreboot w/o any devices under the cpu_cluster device. No more exceptions. Change-Id: I9aedbc0dffc638b878bd0ffacfa318b6eb30d504 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d21e181077eba3c5ee03afca1738a24c21a8fc19 Original-Change-Id: I891aeb36319dce67ce9e431156c85c74177c7ab7 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217511 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9066 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: Replace CONFIG_* variables with {read/write}_currentFurquan Shaikh
Instead of relying on config variables to determine the current el, use {read/write}_current macros for accessing registers. BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully and boots to kernel login prompt Change-Id: I6c27571fa65e06e28b71fee3e21d6ca93542e66b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 96aed53b2879310f6f979d5aa78b8d1df7f04564 Original-Change-Id: If4a5d1e9aa50ab180c8012862e2a6c37384f7f91 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217148 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9065 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64 libhelpers: Add helper functions for writing sp_elxFurquan Shaikh
BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully Change-Id: Id9367b1fc836b7b8c8fd15b372673853493f67d4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 561e9c4ec2b0657846d50bbc893ef7541230f932 Original-Change-Id: Ie950e893b01456c23af14304bd4dd8f61af9f244 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216905 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9064 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64 libhelpers: Add helper functions with el argumentFurquan Shaikh
Allow read/write to registers at a given el. Also, make read/write registers at current el call this newly added function. BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully Change-Id: I98f35b8d3eb5e292ac895102ad91b675325c08c7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 11d90df1fd92e03c25bfc463429a5f6a8d9d411d Original-Change-Id: I17de4c4f3bc1ee804422efe5f4703b4dd65b51f2 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216904 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9063 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: Add support for read and write registers at current EL in assemblyFurquan Shaikh
In order to ease the process of reading and writing any register at current EL, provide read_current and write_current assembly macros. These are included in arch/lib_helpers.h under the __ASSEMBLY__ macro condition. This is done to allow the same header file to be included by .c and .S files. BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully Change-Id: I51749b6e4ae7b1ffbaae28d915cd100a28959f26 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c11c7287f507fa398cbbee75abc2bd11140ef19b Original-Change-Id: I1258850438624abfe3b1ed7240df0db0e7905be6 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216373 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9062 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27smbios: add funtion for smbios type17Kane Chen
Add smbios type 17 which can optionally be implemented at the platform or mainboard level In order to create SMBIOS type17, you will need to fill memory_info data BUG=None BRANCH=None TEST=Compile successfully on rambi and samus Boot to chromeOS on samus and rambi Original-Change-Id: Ie4da89135c879d7a687305d423103fcfcbb96e3f Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210005 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 634b899ba41242caa800d7b570f3a339c738db77) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I61d1e8b1d32d43f0011b0f93966d57646ea0eb63 Reviewed-on: http://review.coreboot.org/8955 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-27mips: Remove superfluous menu entryPatrick Georgi
Change-Id: Iaf8167839f8506bd2ab08c2ba9f8317ba2437f28 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reported-by: Paul Menzel Reviewed-on: http://review.coreboot.org/9054 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-03-27arm64: remove soc_secondary_cpu_init()Aaron Durbin
The original purpose of soc_secondary_cpu_init() was to provide a way for the SoC to run code on the secondary processors as they come up. Now that devicetree based bringup is supported there's no need to have this functionality. BUG=chrome-os-partner:31761 BRANCH=None TEST=Booted SMP into linux. Change-Id: I6fa39b66a8b728d9982b0721480b7fae45af7c6e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1356ec527e2bc61043ccd7dea4a7ff5182b16f3e Original-Change-Id: Ie5c38ef33efadb2d6fdb2f892b4d08f33eee5c42 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216927 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9044 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27armv4: Build in SMP settings with non-SMP armv4 CPUsPatrick Georgi
There are some ARMv8/ARMv4 SoC where the ARMv8 part needs to be SMP aware but the ARMv4 part does not. Until we need real SMP on ARMv4, work around that situation with stub defines. Change-Id: Iec5b4302b19c17fe2b3f677b84a8edf4b4902946 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9046 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: add devicetree based CPU startupAaron Durbin
This adds SMP bring up support for arm64 cpus. It's reliant on DEVICE_PATH_CPU devices in the devicetree. Then for each enabled device it attempts to start then initialize each CPU. Additionally, there is a cpu_action construct which allows for running actions on an individual cpu. BUG=chrome-os-partner:31761 BRANCH=None TEST=Booted both cores on ryu into linux. Change-Id: I3e42fb668034c27808d706427a26be1558ad2af1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a733fd566a8e5793da5ff28f9c16c213f411372e Original-Change-Id: I407eabd0b6985fc4e86de57a9e034548ec8f3d81 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216925 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9042 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: split cpu.h headerAaron Durbin
Add a cpu-internal.h for internal prototypes to the architecture specific code. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built and booted. Change-Id: I12a379f86056a9a2007a7c036d65b5e08e558d0e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5dcd488326f6496d80eb1fe1ff4414ebba1280e9 Original-Change-Id: I8ab520478954a3b43e8e0831d1883f9a791850aa Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216924 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9041 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: add spinlock implementationAaron Durbin
Provide a simple spinlock implentation for arm64. A value of 0 is unlocked and a value of 1 is locked. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built and ran SMP bringup on ryu. Change-Id: Ie88a715a6b51cd38a5fdd830583dae528cc49d67 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 14dab94610c96d6b1530c64d661833f8e613101c Original-Change-Id: I3bf2d80b91112d04442455ff0fa3f16900b7327f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216923 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9040 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: move spinlock.h to proper placeAaron Durbin
The spinlock header file was not residing in the correct place. It needs to live under 'arch/smp'. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built with SMP. spinlock.h found. Change-Id: Ie0e974674a6ea8ec769ca0ce64eb888c4d094652 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 50079befdc3d43306e4ae9e543f7266f1ac99aa0 Original-Change-Id: I0e594cacfafcd6f30802c9563785ca09a2f7a2af Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216922 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9039 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: add more barrier supportAaron Durbin
The load-acquire/store-release operations (including exclusive variants) form a basis for atomic operations. Also remove the dmb, dsb, and isb functions from lib_helpers as barrier.h already included these. Lastly, utilize barrier.h. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built and ran SMP bringup using barriers. Change-Id: I6304a478d769dc2626443005b4eec4325d8a06f4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8fac8d46b09d449d59f1b4f492d363392dcc4118 Original-Change-Id: I77ff160c635297a2c7cab71cb0d3f49f2536f6ff Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216921 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9038 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: remove printk() before console_init()Aaron Durbin
printk() shouldn't be called until the consoles have been initialized. This just so happened to work by luck. Once CONFIG_SMP is enabled that breaks because of spinlock usage in uncached memory. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built with CONFIG_SMP and ramstage doesn't hang early. Change-Id: I54231db3c811c0d19c5c7fbaa406cacd1ff019ec Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 31c3f972ac5c89472009b5b2cb7dbc0f02cfd9a0 Original-Change-Id: I6091b1e949e648b3435231946e5924260bf1807f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216920 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9037 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: update cpu.c licenseAaron Durbin
The code should be GPL. Update accordingly. BUG=chrome-os-partner:31761 BRANCH=None TEST=None Change-Id: I051ceb3f12e9938819b513413aae43cbf51d9b86 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cdff53ebf4c1a1d86d68054c2d25dce45b69ff48 Original-Change-Id: I26a40a239afd851d351dbda0d716ef992b88b6c8 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216428 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9035 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: add midr_el1 accessor functionAaron Durbin
Provide access to the MIDR_EL1 register to obtain the main id for determining CPU implementer and part/revision information. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built and printed the output of this function on ryu. Change-Id: I42cec75072fc5e8b48f63c1971840fdc415e4326 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ad19ffe629d9f16b8fd07051ce73533e97fb3f5c Original-Change-Id: I8b8506ebff8e6f9d7c4f96d7ff7e21803972961e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216423 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9032 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: remove _stack and _estack symbols in linker scriptAaron Durbin
These symbols should have been removed with the stack refactoring. I'm not sure how it was missed. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and booted into kernel with both cpus. Change-Id: Ia6c2103d7b5e2c9d74cdc5d1b5f42f8954812231 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d9432b5cf0cce3bfdbfd5371fb3280e3cc746a42 Original-Change-Id: I17bc9a7aaaf133f427b15f803a6003fa2ca8f8a6 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/215541 Reviewed-on: http://review.coreboot.org/9024 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: provide API for coordinating secondary CPU bringupAaron Durbin
Provides a minimal API for coordinating with the SoC for bringing up the secondary CPUs. There's no eventloop or dispatcher currently nor does it do anything proper when one of the secondary CPUs are brought up. Those decisions are deferred to the SoC. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and brought up 2nd cpu using this API. Change-Id: I8ac0418282e2e5b4ab3abfd21c88f51d704e10f9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5303ae3d6bfc9f8f908fcb890e184eb9b57f1376 Original-Change-Id: I3b7334b7d2df2df093cdc0cbb997e8230d3b2685 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214775 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9019 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: add exception_hwinit()Aaron Durbin
exception_hwinit() provides a path for just setting the hardware state. This allows for other CPUs but the boot CPU for setting up the appropriate vector table. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and booted to the kernel. Change-Id: Ifd44ab697bce5cd351f05069519785dc80e2b866 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 76a1c9cb3df930b28469608ecb5c35be7ccdadd1 Original-Change-Id: Ib09c813b49a4f00daca0b53d9dca972251fcf476 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214773 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9017 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: make mmu_enable() use previous ttb from mmu_init()Aaron Durbin
No need to pass in the same value for the ttb after just calling mmu_init(). All current users are setting this once and forgetting it. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and booted on ryu. Change-Id: Ie446d16eaf4ea65a34a9c76dd7c6c2f9b19c5d57 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bd77461d483b513a569365673c83badc752f4aa8 Original-Change-Id: I54c7e4892d44ea6129429d8a46461d089dd8e2a9 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214772 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9016 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 04:29:33 +0000