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2017-10-16arch/x86/gdt: Correct format of multi-line commentPaul Menzel
Change-Id: I87148315cdf7e420eac2f3f680251f8e963a9707 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/21956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-09-27arch/riscv: hls_init: Initialize time{,cmp} with dummy pointersJonathan Neuschäfer
In current versions of spike, the config string is not available anymore, because RISC-V is moving toward OpenFirmware-derived device trees (either in FDT or text format). Using query_config_string leads to a crash in these versions of spike. With this commit and If0bea4bf52d ("riscv: Update register address"), coreboot reaches the romstage again, on spike. Change-Id: Ib1e6565145f0b2252deb1f4658221a4f816e2af4 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-09-27arch/riscv: Document mprv_{read,write}_* functionsJonathan Neuschäfer
Change-Id: Iaf0cb241f0eb4de241f0983c0b32dbcc28f96480 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-09-27arch/riscv: trap handler: Print load/store access width in bitsJonathan Neuschäfer
This is easier to read than the raw shift amount that's extracted from load/store instructions. Change-Id: Ia16ab9fbaf55345b654ea65e65267ed900eb29e1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-09-26riscv: Update register addresswxjstz
I triggered a bug, when I try to debug riscv code by spike. This bug is caused by an instruction exception[csrwi 0x320,7]. This is operate for mcounteren. This address is error. 0x306 is right. scounteren is not need to be set, because S-mode code controls it. Change-Id: If0bea4bf52d8ad2fb2598724d6feb59dc1b3084a Signed-off-by: wxjstz<wxjstz@126.com> Reviewed-on: https://review.coreboot.org/20043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-09-22arch/x86: Add ebda read/write functions into EBDA librarySubrata Banik
This patch provides new APIs to write into EBDA area and read from EBDA area based on user input structure. Change-Id: I26d5c0ba82c842f0b734a8e0f03abf148737c5c4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-09-22arch/x86: Enable ebda library for romstage and postcarSubrata Banik
This patch provides a kconfig option as EARLY_EBDA_INIT to ensures user can make use of EBDA library even during early boot stages like romstage, postcar. Change-Id: I603800a531f56b6ebd460d5951c35a645fbfe492 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-22arch/x86: Include acpi_s3.c support in postcar stageSubrata Banik
This patch ensures acpi APIs are available for postcar stage. Change-Id: Ia0f83cd4886ba7a16286dbbeb3257ede014ee3c7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13arch/x86: Fix typo with MTRRKyösti Mälkki
Change-Id: I67a470c2c2a659d5355fdd0939d0572c1ff3e291 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-09-08arch/x86/postcar: Support CBMEM_TOP_BACKUPKyösti Mälkki
Boards with CBMEM_TOP_BACKUP=y can also use POSTCAR_STAGE for MTRR setup after adding this file in the build. Change-Id: I5f9a673ff59ccfbba16308d27f653f5cf3b49017 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-08arch/x86 postcar: Fix use with stage_cacheKyösti Mälkki
Postcar failed when loading from stage_cache, if romstage did not pass same pcf->stack on normal and resume paths. Change-Id: I853afb1fbdb942fd671d89950911c850c96e3af3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-06arch/x86/Kconfig: Add deprecation warnings for LATE_CBMEM_INITJonathan Neuschäfer
The deprecation of late (post-romstage) CBMEM initialization was announced in this blog post: https://blogs.coreboot.org/blog/2017/05/08/announcing-coreboot-4-6/ There are two warnings: * In LATE_CBMEM_INIT's help text, I've added a multi-line warning, that aims to explain the problem. * In src/mainboard/Kconfig (just below the mainboard selection), there's a warning which points the user at LATE_CBMEM_INIT, if such a board is selected. Also update the function that needs to be implemented, as pointed out by Keith Hui and Kyösti Mälkki. Change-Id: I2d21a6ab2fc2811d44fc4febb05841bb2f8d1857 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-06ACPI S3: Remove conflicting local acpi_get_sleep_type()Kyösti Mälkki
We now require EARLY_CBMEM_INIT and romstage_handoff to support HAVE_ACPI_RESUME. Thus acpi_handoff_wakeup() would never call an externally defined acpi_get_sleep_type(). Name _sleep_type() was also inapproriate here, as it referred to hardware-dependent SLP_TYP field of PM1CNT but still returned ACPI_Sx value instead. Change-Id: I8dc130f1e86dd7e96922d546f0ae9713188336cd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-09-05Move ADDR32() hack to arch/x86Patrick Georgi
It's arch specific, so no need to pollute non-x86 with it. Change-Id: I99ec76d591789db186e8a33774565e5a04fc4e47 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/21392 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-30acpigen: Add stop gpio control to power resourceFurquan Shaikh
There is at least one I2C device (being used by Soraka) that has 3 controls -- enable, reset and stop. If the stop gpio is not put into the right state when turning off the device in suspend mode, then it causes leakage. Thus, we need control in power resource to be able to stop the device when entering suspend state. BUG=b:64987428 TEST=Verified on soraka that touchscreen stop is correctly configured on suspend. Change-Id: Iae5ec7eb3972c5c7f80956d60d0d3c321bbefb0f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21249 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-30acpi_device: Provide a new function to add a list of propertiesDuncan Laurie
Provide a new function that will allow adding arbitrary properties to devicetree entries without needing a custom driver for the device. This will allow the 'generic i2c' driver to support kernel drivers that need additional device properties exposed and have those board specific properties set with values from devicetree. BUG=b:63413023 TEST=not used yet, compiles cleanly Change-Id: Id272256639a8525406635e168a3db5ab1ba4df6b Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/21269 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-29arch/x86: Add Kconfig option for ACPI \_PR CPU name stringMarc Jones
Add a Kconfig option to change the \PR.CPxx name string. This provides some flexibility when working with table not generated by coreboot. Change-Id: Ibc0c56783c6da80501e2177de96a414b592cb74f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-19i82801dx/gx/ix/jx: Add low-memory backup for S3 pathKyösti Mälkki
SMM relocation code overwrite low memory owned by OS. Change-Id: Ifa3d28bed3d3db65b0707bde62ae2b424a231f1a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19405 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-18include/device: Split i2c.h into threeNico Huber
Split `i2c.h` into three pieces to ease reuse of the generic defi- nitions. No code is changed. * `i2c.h` - keeps the generic definitions * `i2c_simple.h` - holds the current, limited to one controller driver per board, devicetree independent I2C interface * `i2c_bus.h` - will become the devicetree compatible interface for native I2C (e.g. non-SMBus) controllers Change-Id: I382d45c70f9314588663e1284f264f877469c74d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-17arch/x86: Make postcar TempRamExit call genericMarshall Dawson
Move the FSP-specific call for tearing down cache-as-RAM out of postcar.c and replace it with an empty weak function. This patch omits checking if (IS_ENABLED(CONFIG_FSP_CAR)). The temp_ram_exit.c file with the real fsp_temp_ram_exit() is only built when CONFIG_FSP_CAR is true. Change-Id: I9adbb1f2a7b2ff50d9f36d5a3640f63410c09479 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20965 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-10SMBIOS: Correct length calculation for empty string tableKonstantin Aladyshev
If all strings in SMBIOS table are empty, smbios_string_table_len function should return 2, cause every table must end with "\0\0". Also replace "eos" field type in smbios structures from char to u8. Change-Id: Ia3178b0030aa71e1ff11a3fd3d102942f0027eb1 Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com> Reviewed-on: https://review.coreboot.org/20840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-07-26Port cmos.default handling to C environment bootblockNico Huber
Gather related code in the new file drivers/pc80/rtc/mc146818rtc_boot.c, call sanitize_cmos() from C environment bootblock. Change-Id: Ia5c64de208a5986299c0508d0e11eeb8473deef1 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-25src/arch: Fix checkpatch warning: no spaces at the start of a lineMartin Roth
Change-Id: Id9846ceb714dceaea12ea33ce2aa2b8e5bb6f4df Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-24Fix files with multiple newlines at the end.Martin Roth
Change-Id: Iaab26033e947cb9cf299faf1ce6d40a90a9facbe Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20704 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-21arch/arm/armv7: Correct checkpatch errorsLogan Carlson
- Correct whitespace issues with files under arch/arm/armv7. - Fix comments and remove unnecessary line continuations in mmu.c Change-Id: I69d50030b07b1919555feca44967472922176a81 Signed-off-by: Logan Carlson <logancarlson@google.com> Reviewed-on: https://review.coreboot.org/19996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-18arch/x86: select RELOCATABLE_MODULES when POSTCAR is selectedAaron Durbin
The postcar relies on the relocatable modules support. Specifically select that dependency. Change-Id: If19c39c3f153cd5a526fdad6fe09b8c309ef024f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20635 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-17AGESA boards: Fix regressions with LATE_CBMEM_INITKyösti Mälkki
Some configurations of AGESA boards fail to boot after commit 61be360 AGESA: Fix UMA calculations Implementation of cbmem_find() for ENV_ROMSTAGE expects that CBMEM has already been initialized. In the case of LATE_CBMEM_INIT boards, this is not the case and cbmem_top() returned NULL prior to the offending commmit. By definition LATE_CBMEM_INIT does not have known cbmem_top() in ENV_ROMSTAGE except for possible ACPI S3 resume path. Change-Id: Icb8f44661d479e5ad43b123600305dcbc3ce11e1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-13src: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
These are places that were missed on the first pass. Change-Id: Ia6511f0325433ab020946078923bf7ad6f0362a3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20358 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-07-13Rename __attribute__((packed)) --> __packedStefan Reinauer
Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-13arch/x86/assembly_entry: Align stack for car_stage_entryMarshall Dawson
At process _start, the stack is expected to be aligned to a 16-byte boundary. Upon entry to any function the stack frame must have the end of any arguments also aligned. In other words the value of %esp+4 or %rsp+8 is always a multiple of 16 (1). Align the stack down and change the method for executing car_stage_entry from jmp to call which should preserve proper alignment regardless of a 32- or 64-bit build. Although 4-byte alignment is the minimum requirement for i386, some AMD platforms use SSE instructions which expect 16-byte. 1) http://wiki.osdev.org/System_V_ABI See "Initial Stack and Register State" and "The Stack Frame" in the supplements. BUG=chrome-os-partner:62841664 Change-Id: I8a15514f551a8e17e9fe77b8402fe0d2b106972e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-07x86/acpigen: Fix acpigen_write_fieldPatrick Rudolph
The current code doesn't work for field with size > 0x3f. Fix that by using the correct syntax, reverse engineered using iasl. Refactor to reuse existing code. Tested on GNU Linux 4.9 and iasl. Change-Id: Iac3600f184e6bd36a2bcb85753110692fbcbe4b6 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-07-07arch/*: Update Kconfig symbol usageMartin Roth
- Update all symbols to use IS_ENABLED() - Update non-romcc usage to use 'if' instead of '#if' where it makes sense. Change-Id: I5a84414d2d1631e35ac91efb67a0d4c1f673bf85 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20005 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-07-06smbios: Correct the system enclosure typesElyes HAOUAS
Regarding the "System Management BIOS Reference Specification" Version: 3.1.1, Date: 2017-01-12, Laptop system enclosure is 0x09 and for Notebook it is 0x0a Change-Id: I5538be0b434eed20d76aef6f26247e46d1225feb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-29arch/x86: update assembly to ensure 16-byte alignment into CAaron Durbin
When the C compiler expects 16-byte alignment of the stack it is at the call instruction. Correct existing call points from assembly to ensure the stacks are aligned to 16 bytes at the call instruction. Change-Id: Icadd7a1f9284e92aecd99c30cb2acb307823682c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-22arch/x86/smbios: Fix scope of variable declarationNico Huber
Fix up for 1b5eda0 (arch/x86/smbios: Fix undefined behavior) which introduced the variable `tmp` and used it out of scope. Should fix coverity CID 1376385 (Memory - illegal accesses (RETURN_LOCAL)). Change-Id: I8d4f664fc54faf6beb432b939dda4ddf93cf5d3e Found-by: Coverity Scan #1376385 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-22arch/x86: Make rdrand.c clang friendlyStefan Reinauer
rdrand64() is not clang friendly. Actually it looks like the function is incorrect on 32bit x86 for all compilers including gcc, but gcc won't care because the function is never called on x86: src/arch/x86/rdrand.c:51:15: error: invalid output size for constraint '=a' : "=a" (*rand), "=qm" (carry)); ^ 1 error generated. Guard the code correctly if ENV_X86_64 is not set. Change-Id: Ia565897f5e4caaaccfcb02cf1245b150272dff68 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-20arch/x86/smbios: Fix undefined behaviorRyan Salsamendi
Fixes report found by undefined behavior sanitizer. Dereferencing a pointer that's not aligned to the size of access is undefined behavior. The report triggered for smbios_cpu_vendor(). Also fixes the same issue in smbios_processor_name() found by inspection. Change-Id: I1b7d08655edce729e107a5b6e61ee509ebde33b6 Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/20154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-20arch/x86/ebda: Change memcpy() to endian wrappersRyan Salsamendi
Change memcpy()s and memset()s to endian.h wrappers for consistency and safety. Add zero_n() wrapper to safely clear memory. Change-Id: If155d82608c81992f05eae4d2223de6f506e98c5 Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/20240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-14arch/x86: Fix undefined behaviorRyan Salsamendi
Fixes report found by undefined behavior sanitizer. Dereferencing a pointer that is not aligned to the size of access is undefined behavior. Switch to memcpy() for unaligned write to EBDA_LOWMEM. Change other write16()s in setup_ebda() to memcpy() for consistency. Change-Id: I79814bd47a14ec59d84068b11d094dc2531995d9 Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/20132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-08arch/x86/acpigen: Add additional opcodesPatrick Rudolph
Add additional ACPI opcodes, that are going to be used in the following commits. Change-Id: I20c3aa5a1412e5ef68831027137e9ed9e26ddbc9 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-06-07src: change coreboot to lowercaseMartin Roth
The word 'coreboot' should always be written in lowercase, even at the start of a sentence. Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-02arch/arm/include/armv7/arch: Correct keyword organization in cpu.hLogan Carlson
Move the inline keyword in between the static keyword and the return type. Change-Id: Ibacc5ee9fabff7fec2abd5534312cf3ab1bb28cf Signed-off-by: Logan Carlson <logancarlson@google.com> Reviewed-on: https://review.coreboot.org/19991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-02arch/arm: Correct checkpatch errorsLogan Carlson
Correct whitespace issues in arch/arm and arch/arm64. Enclose complex values in parenthesis. Change-Id: I74b68f485adff1e6f0fa433e51e12b59ccea654b Signed-off-by: Logan Carlson <logancarlson@google.com> Reviewed-on: https://review.coreboot.org/19989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-05-30arch: Unify basic cache clearing APIJulius Werner
Caching is a very architecture-specific thing, but most architectures have a cache in general. Therefore it can be useful to have a generic architecture-independent API to perform simple cache management tasks from common code. We have already standardized on the dcache_clean/invalidate naming scheme that originally comes from ARM in libpayload, so let's just do the same for coreboot. Unlike libpayload, there are other things than just DMA coherency we may want to achieve with those functions, so actually implement them for real even on architectures with cache-snooping DMA like x86. (In the future, we may find applications like this in libpayload as well and should probably rethink the API there... maybe move the current functionality to a separate dma_map/unmap API instead. But that's beyond scope of this patch.) Change-Id: I2c1723a287f76cd4118ef38a445339840601aeea Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-30arch/x86: Add function to determine if we're currently running from CARJulius Werner
This patch adds a simple function that can be used to check if CAR_GLOBALs are currently being read from CAR or from DRAM. Change-Id: Ib7ad0896a691ef6e89e622b985417fedc43579c1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-30arm64: Align cache maintenance code with libpayload and ARM32Julius Werner
coreboot and libpayload currently use completely different code to perform a full cache flush on ARM64, with even different function names. The libpayload code is closely inspired by the ARM32 version, so for the sake of overall consistency let's sync coreboot to that. Also align a few other cache management details to work the same way as the corresponding ARM32 parts (such as only flushing but not invalidating the data cache after loading a new stage, which may have a small performance benefit). Change-Id: I9e05b425eeeaa27a447b37f98c0928fed3f74340 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-27CBMEM: Clarify CBMEM_TOP_BACKUP function usageKyösti Mälkki
The deprecated LATE_CBMEM_INIT function is renamed: set_top_of_ram -> set_late_cbmem_top Obscure term top_of_ram is replaced: backup_top_of_ram -> backup_top_of_low_cacheable get_top_of_ram -> restore_top_of_low_cacheable New function that always resolves to CBMEM top boundary, with or without SMM, is named restore_cbmem_top(). Change-Id: I61d20f94840ad61e9fd55976e5aa8c27040b8fb7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-22arch/x86/include: Use IS_ENABLED() macroNico Huber
Change-Id: I0f9a92e595ec765d47f89f0023ff69636ee406af Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19761 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-183rdparty/arm-trusted-firmware: Update to upstream masterMartin Roth
Submodule 3rdparty/arm-trusted-firmware 236c27d21f..3944adca59 This brings in 241 new commits from the upstream arm-trusted-firmware repository, merged to the upstream tree between December 30, 2016 and March 18, 2017. 3944adca Merge pull request #861 from soby-mathew/sm/aarch32_fixes .. e0f083a0 fiptool: Prepare ground for expanding the set of images at runtime Also setup ATF builds so that unused functions don't break the build. They're harmless and they don't filter for these like we do. Change-Id: Ibf5bede79126bcbb62243808a2624d9517015920 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-18CBMEM: Add config CBMEM_TOP_BACKUPKyösti Mälkki
AGESA and binaryPI boards have no easy way to determine correct cbmem_top() location early enough when GFXUMA is enabled, so they will use these functions with EARLY_CBMEM_INIT as well. At the end of AmdInitPost() the decisions of UMA base and size have not been written to hardware yet. The decisions are stored inside AGESA heap object we cannot locate from coreboot proper until after AmdInitEnv(). Modify code such that weak backup functions are only defined for LATE_CBMEM_INIT; they are somewhat troublesome to handle. Change-Id: Ifef4f75b36bc6dee6cd56d1d9164281d9b2a4f2a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19306 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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