Age | Commit message (Expand) | Author |
2016-08-06 | acpi: Generate object for coreboot table region | Duncan Laurie |
2016-08-04 | src/arch/riscv/id.S: Don't hardcode the strings | Jonathan Neuschäfer |
2016-08-03 | ACPI: Add code to create root port entry in DMAR table | Werner Zeh |
2016-08-03 | ACPI: Add code to include ATSR structure in DMAR table | Werner Zeh |
2016-08-02 | arch/riscv: Add include/arch/barrier.h | Jonathan Neuschäfer |
2016-08-01 | Remove non-ascii & unprintable characters | Martin Roth |
2016-08-01 | arch/x86: Enable postcar console | Lee Leahy |
2016-08-01 | arch/x86: Display MTRRs after MTRR update in postcar | Lee Leahy |
2016-07-31 | src/arch: Capitalize CPU, RAM and ROM | Elyes HAOUAS |
2016-07-28 | arch/riscv: Refactor bootblock.S | Jonathan Neuschäfer |
2016-07-28 | arch/riscv: Only initialize virtual memory if it's available | Jonathan Neuschäfer |
2016-07-28 | arch/riscv: Remove spinlock code from atomic.h | Jonathan Neuschäfer |
2016-07-27 | arch/x86: Add bootblock and postcar support for SOC MTRR access | Lee Leahy |
2016-07-26 | arch/x86: Generate a map file for the postcar stage | Lee Leahy |
2016-07-26 | arch/x86: Organize ramstage to match other stages | Lee Leahy |
2016-07-26 | arch/x86: Move romstage files into romstage section | Lee Leahy |
2016-07-26 | arch/x86: Move postcar stage commands into place | Lee Leahy |
2016-07-19 | arch/riscv: Enable unaligned load handling | Jonathan Neuschäfer |
2016-07-18 | arch/riscv: Remove enter_supervisor | Jonathan Neuschäfer |
2016-07-18 | arch/riscv: Change all eret instructions to .word 0x30200073 (mret) | Jonathan Neuschäfer |
2016-07-17 | acpi: Change API called to write the name for ACPI_DP_TYPE_CHILD | Harsha Priya |
2016-07-15 | arch/x86: provide common Intel ACPI hardware definitions | Aaron Durbin |
2016-07-15 | arch/x86: provide common ACPI_Sx constants | Aaron Durbin |
2016-07-14 | spike-riscv: Look for the CBFS in RAM | Jonathan Neuschäfer |
2016-07-14 | arch/riscv: Unconditionally start payloads in machine mode | Jonathan Neuschäfer |
2016-07-08 | acpi: Change device properties to work as a tree | Duncan Laurie |
2016-07-07 | acpigen_write_package: Return pointer to package element counter | Duncan Laurie |
2016-07-02 | acpi_device: Have acpi_device_scope() use a separate buffer | Duncan Laurie |
2016-07-02 | gpio: Add support for translating gpio_t into ACPI pin | Duncan Laurie |
2016-06-28 | riscv/bootblock.S: Register machine-mode, not supervisor-mode trap handler | Jonathan Neuschäfer |
2016-06-28 | arch/riscv: Show fault PC and load address on load access faults | Jonathan Neuschäfer |
2016-06-28 | arch/riscv: Move _start to the beginning of the bootblock | Jonathan Neuschäfer |
2016-06-24 | region: Add writeat and eraseat support | Antonello Dettori |
2016-06-24 | arch/x86/smbios: Correct manufacturer ID | Elyes HAOUAS |
2016-06-22 | ACPI S3: Add common recovery code | Kyösti Mälkki |
2016-06-22 | ACPI S3: Fix prohibited wakeup | Kyösti Mälkki |
2016-06-22 | ACPI S3: Split support for HAVE_ACPI_RESUME | Kyösti Mälkki |
2016-06-22 | ACPI S3: Move SMP trampoline recovery | Kyösti Mälkki |
2016-06-22 | Ignore RAMTOP for MTRRs | Kyösti Mälkki |
2016-06-21 | riscv-spike: Move coreboot to 0x80000000 (2GiB) | Jonathan Neuschäfer |
2016-06-20 | ACPI S3: Cleanup RSDP reference | Kyösti Mälkki |
2016-06-20 | arch/x86/smbios: Add DRAM manufacturer | Patrick Rudolph |
2016-06-17 | Move definitions of HIGH_MEMORY_SAVE | Kyösti Mälkki |
2016-06-17 | Define RAMTOP for x86 only | Kyösti Mälkki |
2016-06-12 | arch/riscv: Compile with -mcmodel=medany | Jonathan Neuschäfer |
2016-06-12 | arch/riscv: Add misc.c to bootblock/romstage to get udelay() | Jonathan Neuschäfer |
2016-06-12 | arch/riscv: copy read/write8/16/32 from x86 | Jonathan Neuschäfer |
2016-06-12 | arch/riscv/trap_util.S: Use "li" pseudo-instruction to load a constant | Jonathan Neuschäfer |
2016-06-11 | arch/x86: Support "weak" BIST and timestamp save routines | Lee Leahy |
2016-06-11 | arch/x86: Add debug spinloops in assembly_entry.S | Lee Leahy |