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AgeCommit message (Expand)Author
2016-09-19arch/x86,lib: make cbmem console work in postcar stageAaron Durbin
2016-09-19arch/x86: move postcar main logic into CAaron Durbin
2016-09-15arch/acpi_ivrs.h: Update 8-byte IVRS entry valuesMartin Roth
2016-09-12src/arch: Improve code formattingElyes HAOUAS
2016-09-12arch/arm: Add armv7-r configurationHakim Giydan
2016-09-12arch/x86: Utilize additional MTRRs in postcar_frame_add_mtrrRizwan Qureshi
2016-09-12arch/x86: Always compile postcar library in romstageRizwan Qureshi
2016-09-07include/arch/acpi.h: change IVRS efr field to iommu_feature_infoMartin Roth
2016-09-07x86/acpi.c: use #define for IVRS revision fieldMartin Roth
2016-09-07arch/x86/include: Add #defines for IVRS tablesMartin Roth
2016-09-04arch/acpi.h: add #if guard to handle the absence of device_t typeAntonello Dettori
2016-08-29arch/riscv: Add missing "break;"Jonathan Neuschäfer
2016-08-28src/arch: Add required space before opening parenthesis '('Elyes HAOUAS
2016-08-28src/arch: Capitalize CPU and ACPIElyes HAOUAS
2016-08-23arch/riscv: Add functions to read/write memory on behalf of supervisor/user modeJonathan Neuschäfer
2016-08-23arch/riscv: Map the kernel space into RAM (2GiB+)Jonathan Neuschäfer
2016-08-23arch/riscv: Implement the SBI againJonathan Neuschäfer
2016-08-23arch/riscv: Enable U-mode/S-mode counters (stime, etc.)Jonathan Neuschäfer
2016-08-23arch/riscv: Fix unaligned memory access emulationJonathan Neuschäfer
2016-08-23arch/riscv: Delegate exceptions to supervisor mode if appropriateJonathan Neuschäfer
2016-08-23arch/riscv: Print the page table structure after constructionJonathan Neuschäfer
2016-08-23arch/arm & arm64: Remove unnecessary whitespace before "\n"Elyes HAOUAS
2016-08-15arch/riscv: Improve and refactor trap handling diagnosticsJonathan Neuschäfer
2016-08-15arch/riscv: Set the stack pointer upon trap entryJonathan Neuschäfer
2016-08-11arch/riscv: Fix the page table setup codeJonathan Neuschäfer
2016-08-11arch/riscv: Update encoding.h and dependent filesJonathan Neuschäfer
2016-08-06acpi: Generate object for coreboot table regionDuncan Laurie
2016-08-04src/arch/riscv/id.S: Don't hardcode the stringsJonathan Neuschäfer
2016-08-03ACPI: Add code to create root port entry in DMAR tableWerner Zeh
2016-08-03ACPI: Add code to include ATSR structure in DMAR tableWerner Zeh
2016-08-02arch/riscv: Add include/arch/barrier.hJonathan Neuschäfer
2016-08-01Remove non-ascii & unprintable charactersMartin Roth
2016-08-01arch/x86: Enable postcar consoleLee Leahy
2016-08-01arch/x86: Display MTRRs after MTRR update in postcarLee Leahy
2016-07-31src/arch: Capitalize CPU, RAM and ROMElyes HAOUAS
2016-07-28arch/riscv: Refactor bootblock.SJonathan Neuschäfer
2016-07-28arch/riscv: Only initialize virtual memory if it's availableJonathan Neuschäfer
2016-07-28arch/riscv: Remove spinlock code from atomic.hJonathan Neuschäfer
2016-07-27arch/x86: Add bootblock and postcar support for SOC MTRR accessLee Leahy
2016-07-26arch/x86: Generate a map file for the postcar stageLee Leahy
2016-07-26arch/x86: Organize ramstage to match other stagesLee Leahy
2016-07-26arch/x86: Move romstage files into romstage sectionLee Leahy
2016-07-26arch/x86: Move postcar stage commands into placeLee Leahy
2016-07-19arch/riscv: Enable unaligned load handlingJonathan Neuschäfer
2016-07-18arch/riscv: Remove enter_supervisorJonathan Neuschäfer
2016-07-18arch/riscv: Change all eret instructions to .word 0x30200073 (mret)Jonathan Neuschäfer
2016-07-17acpi: Change API called to write the name for ACPI_DP_TYPE_CHILDHarsha Priya
2016-07-15arch/x86: provide common Intel ACPI hardware definitionsAaron Durbin
2016-07-15arch/x86: provide common ACPI_Sx constantsAaron Durbin
2016-07-14spike-riscv: Look for the CBFS in RAMJonathan Neuschäfer