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2013-02-14sconfig: rename lapic_cluster -> cpu_clusterStefan Reinauer
The name lapic_cluster is a bit misleading, since the construct is not local APIC specific by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-x86 systems without adding new keywords. Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2377 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14armv7: don't write a forward entry in coreboot tablesDavid Hendricks
We don't seem to need it, and it currently confuses the payload. (credit to Gabe Black for this, I'm just uploading it) Change-Id: I4e3a60eceb9b24e3bc8e50db431c1a731d1cdbae Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/2385 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14sconfig: rename pci_domain -> domainStefan Reinauer
The name pci_domain was a bit misleading, since the construct is only PCI specific in a particular (northbridge/cpu) implementation, but not by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-PCI systems without adding new keywords. Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2376 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-13armv7/exynos: remove some stale files leftover from initial importDavid Hendricks
This removes some files leftover from the initial port. Some are leftover from U-Boot and some were leftover from the skeleton code derived from x86. There's a bit more that we'll get in another sweep. Change-Id: I325793ecb902b3b9430dcf531714ce025d201de6 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2380 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-13armv7: use start and size parameters in mmu_setup()David Hendricks
mmu_setup() was originally written in U-Boot to utilize board-specific global data. Since we're trying to avoid that, we added start and size parameters so that board-specific info can be passed in via mainboard code. Let's start using it that way. Change-Id: I7d7de0e42bd918c9f9f0c177acaf56c110bf8353 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2378 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-02-12armv7: stages.c: Fix grammar: s,The is to,This is to,Paul Menzel
The comment introduced in commit 50c0a50ac6a3fa54ed1286e8b76f933701b6d053 Author: David Hendricks <dhendrix@chromium.org> Date: Thu Jan 31 17:05:50 2013 -0800 armv7: unify stage hand-off routines Reviewed-on: http://review.coreboot.org/2254 contained a typo, which is corrected now. Change-Id: I87f7cfa82fcd12b6961d3329e634b4c201cc047e Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2372 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-12armv7: jump to ELF image using stage_exit()David Hendricks
This is just to get us to the payload. TODO: Do we want to implement any of the stuff from the x86 version, such as copying coreboot to a new location? Change-Id: Ia0544f111d7a1189ebd92d0ba3e11448eabd6252 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2363 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-02-11armv7/exynos5250/snow: deprecate CONFIG_{RAMBASE,RAMTOP}David Hendricks
RAMBASE and RAMTOP are leftovers from the x86 port and do not apply the same way on ARM platforms. On x86 they refer to the low memory region where coreboot tables reside. However on ARM we don't have such a region which is architecturally defined. So instead we'll use the CPU-defined DRAM base address and the mainboard-defined DRAM size. This also has the pleasant side-effect of fixing the coreboot tables to not clobber ramstage code... Change-Id: I5548ecf05e82f9d9ecec8548fabdd99cc1e39c3b Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2351 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-10armv7/exynos5250: place .id between .start and bootblock mainDavid Hendricks
This places the .id section toward the lower region of the coreboot image, before the bootblock. It's easier for humans to find by dumping the image and it also eliminates ID_SECTION_OFFSET which is currently the upper bound on our image size. Change-Id: I7d737b901dac659ddf9aa437cee5dc32f1080546 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2345 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-10armv7: make bootblock linker script more explicitDavid Hendricks
This adds a .bl1 and .start symbol that is placed at the beginning of the .rom section. The goal is to move the .id section in between the reset vector and bootblock_main. Change-Id: Ie732ce656d697c059cc0fa40c844b39f53fc214c Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2344 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-09armv7/exynos: make BL1_SIZE_KB consistent with numbers used...David Hendricks
The Kconfig variable indicates KB, but the number used was bytes. Let's just assume KB is correct for now. Change-Id: I910c126104f0222fc48b70a18df943f2afddeca3 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2341 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-09romcc: Use default romcc flags for most boardsPatrick Georgi
Except for one board, the flags can be derived from CONFIG_MMX and CONFIG_SSE. Change-Id: I64a11135ee7ce8676f3422b2377069a3fa78e24d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2336 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-09romcc: Don't use user overridable romcc flags for bootblockPatrick Georgi
The bootblock is typically run before fpu/mmx/sse setup, so we can't rely on -mcpu=p4 and the like to increase the register space. bootblock_romccflags does that for SSE, but they're controlled separately. Change-Id: I2b0609ac18b2394a319bf9bbbee1f77d2e758127 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2335 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-09armv7: update coreboot tables for armv7David Hendricks
This is a first-pass attempt at cleaning up the coreboot tables for ARM. The most noticable difference is that there is no longer both a high and a low table. Change-Id: I5ba87ad57bf9a697b733511182c0326825071617 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2329 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-09armv7/snow: add BL1_SIZE_KB and get rid of magic constantsDavid Hendricks
This adds a BL1_SIZE_KB config variable so that we can get rid of some magic constants. Change-Id: I9dbcfb407d3f8e367be5d943e95b032ce88b0ad0 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2332 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-09armv7: include $(obj)/config.h when building bootblockDavid Hendricks
Explicitly including it allows us to get rid of some magic constants in the bootblock linker script. Change-Id: I095899babc997addce6b383f00e5ebf135e99d5e Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2331 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-08armv7: Use same console initialization procedure for all ARM stagesHung-Te Lin
Use same console initialization procedure for all ARM stages (bootblock, romstage, and ramstage): #include <console/console.h> ... console_init() ... printk(level, format, ...) Verified to boot on armv7/snow with console messages in all stages. Change-Id: Idd689219035e67450ea133838a2ca02f8d74557e Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2301 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-08console: Only print romstage messages with EARLY_CONSOLE enabled.Hung-Te Lin
Revise console source file dependency (especially for EARLY_CONSOLE) and interpret printk/console_init according to EARLY_CONSOLE setting (no-ops if EARLY_CONSOLE is not defined). Verified to boot on x86/qemu and armv7/snow. Disabling EARLY_CONSOLE correctly stops romstage messages on x86/qemu (armv7/snow needs more changes to work). Change-Id: Idbbd3a26bc1135c9d3ae282aad486961fb60e0ea Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2300 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-08console: Revise serial console configuration names.Hung-Te Lin
The console drivers (especially serial drivers) in Kconfig were named in different styles. This change will rename configuration names to a better naming style. - EARLY_CONSOLE: Enable output in pre-ram stage. (Renamed from EARLY_SERIAL_CONSOLE because it also supports non-serial) - CONSOLE_SERIAL: Enable serial output console, from one of the serial drivers. (Renamed from SERIAL_CONSOLE because other non-serial drivers are named as CONSOLE_XXX like CONSOLE_CBMEM) - CONSOLE_SERIAL_UART: Device-specific UART driver. (Renamed from CONSOLE_SERIAL_NONSTANDARD_MEM because it may be not memory-mapped) - HAVE_UART_SPECIAL: A dependency for CONSOLE_SERIAL_UART. Verified to boot on x86/qemu and armv7/snow, and still seeing console messages in romstage for both platforms. Change-Id: I4bea3c8fea05bbb7d78df6bc22f82414ac66f973 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2299 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-07armv7: Clean up arm/snow bootblock build process.Hung-Te Lin
Remove duplicated / testing code and share more driver for bootblock, romstage and ramstage. The __PRE_RAM__ is now also defined in bootblock build stage, since bootblock is executed before RAM is initialized. Change-Id: I4f5469b1545631eee1cf9f2f5df93cbe3a58268b Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2282 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-06armv7: Clean up: remove deprecated SPL.Hung-Te Lin
"SPL" from U-Boot is deprecated by bootblock in coreboot/arm, so we don't need it anymore. Change-Id: Id16877075d0b870839a10160073ad70777a2af0a Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2297 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-06armv7: Clean up: replace hang() by hlt().Hung-Te Lin
hang() is the legacy function from U-boot and should be replaced by hlt() in coreboot. Change-Id: I0f390b1b6f9ff71487ea36cf16c462724b66d8ca Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2298 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-06bootblock: Reduce register loadPatrick Georgi
The common part of the bootblock resets the nvram data if it's found to be invalid. Since that code is compiled with romcc in i386 mode, there's a shortage on registers. Try to reduce the strain by doing things smarter: cmos_write_inner is the same as cmos_write, just that it doesn't check if the RTC is disabled. Since we just disabled it before, we can assume that it is so. Change-Id: Ic85eb2a5df949d1c1aff654bc1b40d6f2ff71756 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2296 Tested-by: build bot (Jenkins) Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2013-02-06armv7: Prevent CBFS data overlapping bootblock.Hung-Te Lin
For arm/snow, current bootblock is larger than previously assigned CBFS offset and will fail to boot. To prevent this happening again in future, cbfstool now checks if CBFS will overlap bootblock. A sample error message: E: Bootblock (0x0+0x71d4) overlap CBFS data (0x5000) E: Failed to create build/coreboot.pre1.tmp. arm/snow offset is also enlarged and moved to Kconfig variable. Change-Id: I4556aef27ff716556040312ae8ccb78078abc82d Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2295 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-05Don't add another Kconfig special case for TianoStefan Reinauer
We don't need a special Kconfig variable anymore because the FV _is_ the payload, unlike with the old tianocoreboot implementation. Change-Id: I349b5a95783e4146e3ab7f926871188cf2021935 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2284 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-02-05cbfstool: support parsing UEFI firmware volumesStefan Reinauer
This removes the hack implemented in http://review.coreboot.org/#/c/2280 (and should make using 64bit Tiano easier, but that's not yet supported) Change-Id: Ie30129c4102dfbd41584177f39057b31f5a937fd Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2281 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-05cbfstool: Use cbfs_image API for "create" command.Hung-Te Lin
Usage Changes: To support platforms with different memory layout, "create" takes two extra optional parameters: "-b": base address (or offset) for bootblock. When omitted, put bootblock in end of ROM (x86 style). "-H": header offset. When omitted, put header right before bootblock, and update a top-aligned virtual address reference in end of ROM. Example: (can be found in ARM MAkefile): cbfstool coreboot.rom create -m armv7 -s 4096K -B bootblock.bin \ -a 64 -b 0x0000 -H 0x2040 -o 0x5000 Verified to boot on ARM (Snow) and X86 (QEMU). Change-Id: Ida2a9e32f9a459787b577db5e6581550d9d7017b Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2214 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-05cbfstool: Use cbfs_image API for "locate" command.Hung-Te Lin
To support platforms without top-aligned address mapping like ARM, "locate" command now outputs platform independent ROM offset by default. To retrieve x86 style top-aligned virtual address, add "-T". To test: cbfstool coreboot.rom locate -f stage -n stage -a 0x100000 -T # Example output: 0xffffdc10 Change-Id: I474703c4197b36524b75407a91faab1194edc64d Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2213 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-04Hook up corebootPkg as Tianocore payloadPatrick Georgi
This unplugs Stefan's PIANO project. Change Tianocore payload configuration to use corebootPkg. As argument you have to give it the COREBOOT.FD generated by the Tianocore build system. It automatically determines base address and entry point. Compression setting is honored (ie. no compression if you don't want), but corebootPkg currently assumes that coreboot is doing it. Loading a 6MB payload into CBFS without compression will fail more often than not. Change-Id: If9c64c9adb4a846a677c8af40f149ce697059ee6 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2280 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-04smbios: show CONFIG_LOCALVERSION in DMI bios_versionChristian Gmeiner
If somebody makes use of CONFIG_LOCALVERSION show this user provided config string for DMI bios_version. As requested I have attached example output. CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" CONFIG_COMPILER_GCC=y ... root@OT:~# cat /sys/class/dmi/id/bios_version 4.0-3360-g5be6673-dirty CONFIG_LOCALVERSION="V1.01.02 Beta" CONFIG_CBFS_PREFIX="fallback" CONFIG_COMPILER_GCC=y ... root@OT:~# cat /sys/class/dmi/id/bios_version V1.01.02 Beta Change-Id: I5640b72b56887ddf85113efa9ff23df9d4c7eb86 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/2279 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-04exynos/snow: partial clean-up of snow bootblock using build classDavid Hendricks
This removes some duplicate code from Snow's mainboard bootblock by utilizing the bootblock build class. Change-Id: I153247370a8c5127260082dcdca3ebdc5e104fb8 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2270 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-03armv7: Add 'bootblock' build class.Hung-Te Lin
For ARM platform, the bootblock may need more C source files to initialize UART / SPI for loading romstage. To preventing making complex and implicit dependency by using #include inside bootblock.c, we should add a new build class "bootblock". Also #ifdef __BOOT_BLOCK__ can be used to detect if the source is being compiled for boot block. For x86, the bootblock is limited to fewer assembly files so it's not using this class. (Some files shared by x86 and arm in top level or lib are also changed but nothing should be changed in x86 build process.) Change-Id: Ia81bccc366d2082397d133d9245f7ecb33b8bc8b Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2252 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-02-01armv7: Fix entry point in ram stage.Hung-Te Lin
Eliminate the warning message: ld: warning: cannot find entry symbol _start; defaulting to 040000000 The "_start" from c_start.S is deprecated so we need to define entry point again in link description file. Change-Id: I174428faa2e7f08cd91fe96a53e6efea9dc3634e Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2258 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-01clean-up for arch/armv7/Makefile.incDavid Hendricks
This removes a few lines which are obsolete or unneeded. We may want to do something with SMP eventually (can we use it for decompression?) but for now we'll assume non-bootstrap cores are idle until the OS does something with them. Change-Id: Iff6b196e008e803bcfd00e5de07cf471bd2357ea Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2257 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-01armv7: unify stage hand-off routinesDavid Hendricks
This replaces the current stage-specific exit/entry functions with generic versions. Now all stages compile with stage_entry(), which is placed at .text.stage_entry.armv7, and stage_exit(). Snow's ramstage files are also updated to avoid build breakage. Change-Id: I953a2c4b8121bd4b66c3362557997a9ca3aa53b0 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2254 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-01-30armv7: don't hang on divide by zeroRonald G. Minnich
People make mistakes. Hanging the box is not a good reason to kill the firmware, esp. since this is probably happening in a printk. The only issue with the recursive call to printk is that we may deadlock if we have locked something. But we can at least try. Hanging is certainly not what we want ... Change-Id: Ib3bc87bc395ae89e115cf6d042f4167856422ca1 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2233 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2013-01-30Extend CBFS to support arbitrary ROM source media.Hung-Te Lin
Summary: Isolate CBFS underlying I/O to board/arch-specific implementations as "media stream", to allow loading and booting romstage on non-x86. CBFS functions now all take a new "media source" parameter; use CBFS_DEFAULT_MEDIA if you simply want to load from main firmware. API Changes: cbfs_find => cbfs_get_file. cbfs_find_file => cbfs_get_file_content. cbfs_get_file => cbfs_get_file_content with correct type. CBFS used to work only on memory-mapped ROM (all x86). For platforms like ARM, the ROM may come from USB, UART, or SPI -- any serial devices and not available for memory mapping. To support these devices (and allowing CBFS to read from multiple source at the same time), CBFS operations are now virtual-ized into "cbfs_media". To simplify porting existing code, every media source must support both "reading into pre-allocated memory (read)" and "read and return an allocated buffer (map)". For devices without native memory-mapped ROM, "cbfs_simple_buffer*" provides simple memory mapping simulation. Every CBFS function now takes a cbfs_media* as parameter. CBFS_DEFAULT_MEDIA is defined for CBFS functions to automatically initialize a per-board default media (CBFS will internally calls init_default_cbfs_media). Also revised CBFS function names relying on memory mapped backend (ex, "cbfs_find" => actually loads files). Now we only have two getters: struct cbfs_file *entry = cbfs_get_file(media, name); void *data = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, name, type); Test results: - Verified to work on x86/qemu. - Compiles on ARM, and follow up commit will provide working SPI driver. Change-Id: Iac911ded25a6f2feffbf3101a81364625bb07746 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2182 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-30Project PIANO aka tianocorebootStefan Reinauer
This is a Tiano Core loader payload based on libpayload. It will load a Tiano Core DXE core from an UEFI firmware volume stored in CBFS. Currently Tiano Core dies because it does not find all the UEFI services it needs: coreboot-4.0-3316-gc5c9ff8-dirty Mon Jan 28 15:37:12 PST 2013 starting... [..] Tiano Core Loader v1.0 Copyright (C) 2013 Google Inc. All rights reserved. Memory Map (5 entries): 1. 0000000000000000 - 0000000000000fff [10] 2. 0000000000001000 - 000000000009ffff [01] 3. 00000000000c0000 - 0000000003ebffff [01] 4. 0000000003ec0000 - 0000000003ffffff [10] 5. 00000000ff800000 - 00000000ffffffff [02] DXE code: 03e80000 DXE stack: 03e60000 HOB list: 03d5c000 Found UEFI firmware volume. GUID: 8c8ce578-8a3d-4f1c-9935-896185c32dd3 length: 0x0000000000260000 Found DXE core at 0xffc14e0c Section 0: .text size=000158a0 rva=00000240 in file=000158a0/00000240 flags=60000020 Section 1: .data size=00006820 rva=00015ae0 in file=00006820/00015ae0 flags=c0000040 Section 2: .reloc size=000010a0 rva=0001c300 in file=000010a0/0001c300 flags=42000040 Jumping to DXE core at 0x3e80000 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 3E96708 HOBLIST address in DXE = 0x3E56010 Memory Allocation 0x00000003 0x3E80000 - 0x3EBFFFF FV Hob 0xFFC14D78 - 0xFFE74D77 InstallProtocolInterface: D8117CFE-94A6-11D4-9A3A-0090273FC14D 3E95EA0 InstallProtocolInterface: EE4E5898-3914-4259-9D6E-DC7BD79403CF 3E9630C Security Arch Protocol not present!! CPU Arch Protocol not present!! Metronome Arch Protocol not present!! Timer Arch Protocol not present!! Bds Arch Protocol not present!! Watchdog Timer Arch Protocol not present!! Runtime Arch Protocol not present!! Variable Arch Protocol not present!! Variable Write Arch Protocol not present!! Capsule Arch Protocol not present!! Monotonic Counter Arch Protocol not present!! Reset Arch Protocol not present!! Real Time Clock Arch Protocol not present!! ASSERT_EFI_ERROR (Status = Not Found) ASSERT /home/reinauer/svn/Tiano/edk2/MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c(461): !EFI_ERROR (Status) Change-Id: I14068e9a28ff67ab1bf03105d56dab2e8be7b230 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2154 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-29cbfstool: Change "locate" output to prefix "0x".Hung-Te Lin
Currently "cbfstool locate" outputs a hex number without "0x" prefix. This makes extra step (prefix 0x, and then generate another temp file) in build process, and may be a problem when we want to allow changing its output format (ex, using decimal). Adding the "0x" in cbfstool itself should be better. Change-Id: I639bb8f192a756883c9c4b2d11af6bc166c7811d Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2201 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-01-29armv7: Clean up the mmu setup a bitRonald G. Minnich
The previous incarnation did not use all of mmu_setup, which meant we did not carefully disable things before (possibly) changing them. This code is tested and works, and it's a bit of a simplification. Change-Id: I0560f9b8e25f31cd90e34304d6ec987fc5c87699 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2204 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2013-01-29armv7: nuke global_data.h and remove some references to gd structDavid Hendricks
This begins to remove references to global data which u-boot used. There are still many commented out references to gd-> and bd-> which we'll fix once we're happy with the replacements. Change-Id: Ie1b40a997e28a118f8f3ad96a2f9a2462d32fbe3 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2210 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-29armv7: Clean out weak symbols and unnecessary #ifdef's in cache filesDavid Hendricks
This just removes unused code. If for some reason we don't want to initialize cache, then the CPU or mainboard specific init routines don't need to call these. Change-Id: Ieb7393b6cbc103e490753da4ed27114156466ded Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2209 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-01-27ioapic: Factor out counting code to `ioapic_interrupt_count`Patrick Georgi
No need to keep duplicate variants of counting ioapic interrupts. Change-Id: I512860297309c46e05cc5379bf61479878817b1e Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2185 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-01-23clear_ioapic: Fix reading of number of interrupts for IO-APICsAladyshev Konstantin
Apply the same fix for `setup_ioapic` as done in the following commit. commit 23c046b6f16805ff0131460189967bf261d704de Author: Nico Huber <nico.huber@secunet.com> Date: Mon Sep 24 10:48:43 2012 +0200 Fix reading of number of interrupts for IO-APICs The number read from the io-apic register represents the index of the highest interrupt redirection entry, i.e. the number of interrupts minus one. Change-Id: I54c992e4ff400de24bb9fef5d82251078f92c588 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1624 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: I7b730d016a514c95c3b32aee6f31bd3d7b2c08cb Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2043 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-01-22armv7: add ARM-encoded bootblock_exit() stubDavid Hendricks
This replaces the call() function with a stub which is compiled separately using -marm. See http://review.coreboot.org/#/c/2175/ for details. Change-Id: I7f8c45b5e63ec97b0a82294488129d1c97ec0cbf Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2180 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-19armv7/snow: get to romstageDavid Hendricks
This patch does a few things to get us into romstage: - Add romstage as a stage (a later patch adds it as a binary, which is probably wrong). The Makefile magic is complex enough that we let it build the XIP file for now, but we no longer use it. - Replace findstage with loadstage. Loadstage will find a stage, load the code to memory, and zero the remaining part of memory. Now we can link the romstage to go anywhere! - Eliminate magic offsets from code/ldscripts and centralize Kconfig variables in src/cpu/samsung/exynos5250/Kconfig. - Tidy up code and serial output Change-Id: Iae4d2f9e7f429cb1df15d49daf9a08b88d75d79d Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2174 Tested-by: build bot (Jenkins)
2013-01-18armv7: add a wrapper for romstage's main() for ARM ISAGabe Black
This adds a wrapper around main() in romstage which is compiled using -marm. This assumes that the bootblock branches to romstage in ARM mode. The long-term idea is to enforce ABI compatibility when handing off to the next stage by using shims which are which are compiled in a pre- determiend manner and leave the main portions of each stage up to whatever the compiler wants. So it will eventually look like this: 1. bootblock_main (ARM/Thumb) 2. bootblock_exit (ARM) 3. romstage_entry (ARM) 4. romstage_main (ARM/Thumb) (credit to Gabe Black for writing the patch, I'm just uploading it) Change-Id: I4fdb8d2c6c2c0a7178bcb9154c378ddce0567309 Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/2175 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-18Snow bootblock (bloated/debug version)David Hendricks
This is the bloated Snow bootblock which includes: - SPI driver - UART, including requisite I2C, Maxim PMIC, and clock config code. - Adjustments for magic offsets (id section, stack pointer address) This is just a temporary solution until we have romstage loading. Once that happens, we'll rip out all but the code necessary for copying SPI ROM content into SRAM. Change-Id: I2a11e272eb9b6f626b5d9783eabb4a720a1d06be Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2170 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-17Fix the stack setup code so we can use an arbitrary 32-bit valueRonald G. Minnich
We've had obscure errors as the size of the bootblock changes. This fix allows us to use a 32-bit constant. Please test on real hardware before you ack. Change-Id: Ic3d9f4763554bd6104ae9c4ce5bbacd17b40872c Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2168 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-01-17make main() in snow's romstage.c our romstage entry pointDavid Hendricks
Our earlier attempt was jumping straight from asm to the old u-boot board_init_f in lowlevel_init_c.c. We are getting ready to transition to using a real bootblock for ARM, so add romstage.c to the files compiled and we'll make main() our entry point. This also updates romstage.ld to place main() (*(.text.startup)) at the beginning of romstage. Change-Id: Ifc77a6bfba27d915c4cad62c6c8040665294628a Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2163 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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