| Age | Commit message (Expand) | Author |
|---|
| 2016-09-19 | arch/x86: move postcar main logic into C | Aaron Durbin |
| 2016-09-15 | arch/acpi_ivrs.h: Update 8-byte IVRS entry values | Martin Roth |
| 2016-09-12 | src/arch: Improve code formatting | Elyes HAOUAS |
| 2016-09-12 | arch/arm: Add armv7-r configuration | Hakim Giydan |
| 2016-09-12 | arch/x86: Utilize additional MTRRs in postcar_frame_add_mtrr | Rizwan Qureshi |
| 2016-09-12 | arch/x86: Always compile postcar library in romstage | Rizwan Qureshi |
| 2016-09-07 | include/arch/acpi.h: change IVRS efr field to iommu_feature_info | Martin Roth |
| 2016-09-07 | x86/acpi.c: use #define for IVRS revision field | Martin Roth |
| 2016-09-07 | arch/x86/include: Add #defines for IVRS tables | Martin Roth |
| 2016-09-04 | arch/acpi.h: add #if guard to handle the absence of device_t type | Antonello Dettori |
| 2016-08-29 | arch/riscv: Add missing "break;" | Jonathan Neuschäfer |
| 2016-08-28 | src/arch: Add required space before opening parenthesis '(' | Elyes HAOUAS |
| 2016-08-28 | src/arch: Capitalize CPU and ACPI | Elyes HAOUAS |
| 2016-08-23 | arch/riscv: Add functions to read/write memory on behalf of supervisor/user mode | Jonathan Neuschäfer |
| 2016-08-23 | arch/riscv: Map the kernel space into RAM (2GiB+) | Jonathan Neuschäfer |
| 2016-08-23 | arch/riscv: Implement the SBI again | Jonathan Neuschäfer |
| 2016-08-23 | arch/riscv: Enable U-mode/S-mode counters (stime, etc.) | Jonathan Neuschäfer |
| 2016-08-23 | arch/riscv: Fix unaligned memory access emulation | Jonathan Neuschäfer |
| 2016-08-23 | arch/riscv: Delegate exceptions to supervisor mode if appropriate | Jonathan Neuschäfer |
| 2016-08-23 | arch/riscv: Print the page table structure after construction | Jonathan Neuschäfer |
| 2016-08-23 | arch/arm & arm64: Remove unnecessary whitespace before "\n" | Elyes HAOUAS |
| 2016-08-15 | arch/riscv: Improve and refactor trap handling diagnostics | Jonathan Neuschäfer |
| 2016-08-15 | arch/riscv: Set the stack pointer upon trap entry | Jonathan Neuschäfer |
| 2016-08-11 | arch/riscv: Fix the page table setup code | Jonathan Neuschäfer |
| 2016-08-11 | arch/riscv: Update encoding.h and dependent files | Jonathan Neuschäfer |
| 2016-08-06 | acpi: Generate object for coreboot table region | Duncan Laurie |
| 2016-08-04 | src/arch/riscv/id.S: Don't hardcode the strings | Jonathan Neuschäfer |
| 2016-08-03 | ACPI: Add code to create root port entry in DMAR table | Werner Zeh |
| 2016-08-03 | ACPI: Add code to include ATSR structure in DMAR table | Werner Zeh |
| 2016-08-02 | arch/riscv: Add include/arch/barrier.h | Jonathan Neuschäfer |
| 2016-08-01 | Remove non-ascii & unprintable characters | Martin Roth |
| 2016-08-01 | arch/x86: Enable postcar console | Lee Leahy |
| 2016-08-01 | arch/x86: Display MTRRs after MTRR update in postcar | Lee Leahy |
| 2016-07-31 | src/arch: Capitalize CPU, RAM and ROM | Elyes HAOUAS |
| 2016-07-28 | arch/riscv: Refactor bootblock.S | Jonathan Neuschäfer |
| 2016-07-28 | arch/riscv: Only initialize virtual memory if it's available | Jonathan Neuschäfer |
| 2016-07-28 | arch/riscv: Remove spinlock code from atomic.h | Jonathan Neuschäfer |
| 2016-07-27 | arch/x86: Add bootblock and postcar support for SOC MTRR access | Lee Leahy |
| 2016-07-26 | arch/x86: Generate a map file for the postcar stage | Lee Leahy |
| 2016-07-26 | arch/x86: Organize ramstage to match other stages | Lee Leahy |
| 2016-07-26 | arch/x86: Move romstage files into romstage section | Lee Leahy |
| 2016-07-26 | arch/x86: Move postcar stage commands into place | Lee Leahy |
| 2016-07-19 | arch/riscv: Enable unaligned load handling | Jonathan Neuschäfer |
| 2016-07-18 | arch/riscv: Remove enter_supervisor | Jonathan Neuschäfer |
| 2016-07-18 | arch/riscv: Change all eret instructions to .word 0x30200073 (mret) | Jonathan Neuschäfer |
| 2016-07-17 | acpi: Change API called to write the name for ACPI_DP_TYPE_CHILD | Harsha Priya |
| 2016-07-15 | arch/x86: provide common Intel ACPI hardware definitions | Aaron Durbin |
| 2016-07-15 | arch/x86: provide common ACPI_Sx constants | Aaron Durbin |
| 2016-07-14 | spike-riscv: Look for the CBFS in RAM | Jonathan Neuschäfer |
| 2016-07-14 | arch/riscv: Unconditionally start payloads in machine mode | Jonathan Neuschäfer |
