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2019-06-21arch/x86/acpi: use ALIGN_UP instead of ALIGNFelix Held
The ALIGN_UP macro is basically an alias of the ALIGN macro; with this change it's more obvious in which direction the alignment happens. Change-Id: I6f1b9f9bbcafeb85a6ef5c10ce4b57edc0740e72 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2019-06-21arch/arm/cpu: use ALIGN_UP instead of ALIGN for better readabilityFelix Held
Change-Id: Id0e281ece0a647721c18402029cd6980f75d5908 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-06-21arch/x86: use ALIGN_UP instead of ALIGN for better readabilityFelix Held
This patch contains the rest of the fixes for this subtree; having one change for every area would create an unnecessary amouint of patches. Change-Id: Id92c11d58693292d58cba323c8468db858becfb5 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33630 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21arch/x86/tables: use ALIGN_UP instead of ALIGN for better readabilityFelix Held
Change-Id: Idfb814abee87d52d0f5970ec0cd291f738631320 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33629 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21arch-x86/smbios: use ALIGN_UP instead of ALIGN for better readabilityFelix Held
ALIGN_UP is an alias for ALIGN. Change-Id: Ie723ebe80f8f627021151413cb43adce6c88a0dc Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33628 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21fit: Refactor config node handlingJulius Werner
This patch makes some minor refactoring to the way the FIT parser handles config nodes. A lot of this code was written in the dawn age of depthcharge when its device tree library wasn't as well-stocked yet, so some of it can be rewritten nicer with more high-level primitives. There's no point in storing both the string name and the actual FDT node of a FIT image node separately, since the latter also contains the former, so remove that. Also eliminate code for the case of not having an FDT (which makes no sense), and move some more FDT validity/compat checking into fit_update_compat() (mostly in anticipation of later changes). This patch was adapted from depthcharge's http://crosreview.com/1553456 with a couple of modifications specific to coreboot's custom FIT loading code. Change-Id: Ia79e0fd0e1159c4aca64c453b82a0379b133350d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32870 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21arch/x86/cpu: Add define and strings for HygonJinke Fan
Chengdu Haiguang IC Design Co., Ltd (Hygon) is a Joint Venture between AMD and Haiguang Information Technology Co.,Ltd., aims at providing high performance x86 processor for China server market. Its first generation processor codename is Dhyana, which originates from AMD technology and shares most of the architecture with AMD's family 17h, but with different CPU Vendor ID ("HygonGenuine") /Family series number (Family 18h). More details can be found on: http://lkml.kernel.org/r/5ce86123a7b9dad925ac583d88d2f921040e859b.1538583282.git.puwen@hygon.cn Change-Id: I8af8b0f0675f978ac07522029696e43651a3153f Signed-off-by: Jinke Fan <fanjinke@hygon.cn> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32876 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21arch/x86/rdrand.c: Remove unneeded 'else'Elyes HAOUAS
'else' is not needed after a 'break' or 'return'. Change-Id: Ib7bdefb0027a35de42f6a665b98f9e5a2791061f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Vlado Cibic Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-19src/arch/x86/smbios: Change SMBIOS Version to 2.8Christian Walter
Change the SMBIOS Version from 2.7 to 2.8. Necessary changes were already pushed in https://review.coreboot.org/c/coreboot/+/33031 Change-Id: I237cdee7d43e814397b958e4cf941bf58949088d Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-06-19acpi: Add SPMI tablePatrick Rudolph
Add the SPMI table as defined in the IPMI spec v2: https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf Tested on Wedge100s. Change-Id: Idff5134ce4c124f7e76acb0080da404b0c0dfffe Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33487 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-17arm64: make comment match codeMarty E. Plummer
Change-Id: I37b8d5715cb6a32d4853e77098094cd5cffb9a4c Signed-off-by: Marty E. Plummer <hanetzer@startmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-173rdparty/blobs: Update submodule, SNB improvementsArthur Heymans
The sandybridge systemagent-r6 blob is modified: - To be more flexible about the location of the stack w.r.t. the heap - Place the MRC pool right below the MRC_VAR region - to work with the same DCACHE_RAM_BASE from the native raminit (could make the CAR linker symbols easily compatible if desired) This allows CAR setup compatibility between mrc.bin and native bootpath and also allows for BIOS/memory mappeds region larger than 8MB. This changes the semantics of CONFIG_DACHE_RAM_MRC_VAR_SIZE to also include the pool on top of MRC_VAR region. TESTED on T520 (boots and resumes from S3 with mrc.bin). Change-Id: I17d240656575b69a24718d90e4f2d2b7339d05a7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33228 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-15arch/x86/Kconfig: hide the "Bootblock behaviour" option on non-romccArthur Heymans
Selecting which cbfs prefix to load is only implemented with the romcc bootblock. Change-Id: I09523b94605f00ab15b5f0ea3986ac08e3a6afc6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-15arch/x86/Kconfig: Hide the prefix option on all but BOOTBLOCK_NORMALArthur Heymans
Change-Id: Icf5e8fa18bea1cdfb85b8a4999d8fccea94d16b9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-13stage_cache: Make empty inline function if CONFIG_NO_STAGE_CACHE enableSubrata Banik
This patch removes CONFIG_NO_STAGE_CACHE check from caller function and add empty inline function incase CONFIG_NO_STAGE_CACHE is enable. Change-Id: I8e10ef2d261f9b204cecbeae6f65fda037753534 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-09acpigen: Add support for IndexFieldPatrick Rudolph
Add support for generating IndexField, which is similar to Field. Change-Id: If66a627e64953696b0b68488256bd5c141e4c205 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33032 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06Makefile.inc: Compile smm files independent ARCH_RAMSTAGE_X86_32/64Subrata Banik
This patch makes smm related files compile independent of ramstage getting compiled. If user selects RAMPAYLOAD to boot without ramstage, there will be need for smm code to get compiled independently. Change-Id: I17a3eb80a4d5ef86e0319357c01b6bf5b90ef15b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33115 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06src/soc/intel/common/smbios: Add addtional infos to dimm_infoChristian Walter
Add ECC Support and VDD Voltage to dimm_info struct. Now Bus Width and ECCSupport will be propagated correctly in SMBIOS Type 17 Entry. Change-Id: Ic6f0d4b223f1490ec7aa71a6105603635b514021 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33031 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-05src/arch/x86: Prevent attack on null pointer dereferenceJohn Zhao
Clang Static Analyzer version 8.0.0 detects null pointer argument in call to memory copy function. Add sanity check for pointer header to prevent null pointer dereference. TEST=Built and boot up to kernel. Change-Id: I7027b7cae3009a5481048bfa0536a6cbd9bef683 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-04arch/riscv/Kconfig: Make correct default value for CONFIG_ARCH_RISCV_MSubrata Banik
Change-Id: Ib9329904060cab48d527de1b1ccdab5b6fe71b99 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33144 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-02Makefile.inc: Remove unnecessary CONFIG dependencySubrata Banik
This patch removes unnecessary kconfig depencies as below 1. CONFIG_ARCH_RAMSTAGE_X86_32 2. CONFIG_RELOCATABLE_RAMSTAGE Include required files as is without specify kconfig option. Change-Id: Ic9d1a95e80178775dd78e756f97f6da13a24dc95 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2019-05-29src/{include,arch,cpu,lib}: Add missing 'include <types.h>'Elyes HAOUAS
<types.h> is supposed to provide <stdint.h> and <stddef.h>. So when <types.h> is included, <stdint.h> and/or <stddef.h> is removed. Change-Id: I57aead27806e307b9827fc7ee2cd663f12ee6e5e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-29arch/x86: Do not add properties to null DP packagesJacob Garber
It doesn't make sense to add a property to a non-existent Device Property package. However, some of these functions will proceed anyway and allocate a new Device Property package, add the property to that, and then immediately leak the new package. This changes all the acpi_dp_add_* functions to ignore a null package. Change-Id: I664dcdbaa6b1b8a3aeb9a0126d622e2ffb736efd Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 135745{6,7}, 138029{2-6} Reviewed-on: https://review.coreboot.org/c/coreboot/+/32971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-28src/arch/x86: Add automatic type41 entry creationChristian Walter
SMBIOS Type41 Entries will be automatically created. Type 41 entries define attributes of the onboard devices. Change-Id: Idcb3532a5c05666d6613af4f303df85f4f1f6e97 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32910 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-23src/mainboard/google: Adopt Mainboards to changed Type41 FuncChristian Walter
Required for automatic onboard device detection in the next patch. Change-Id: I3087de779faf8d006510c460b5372b22ae54b887 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32909 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-22post_code: add post code for failure to load next stageKeith Short
Add a new post code, POST_INVALID_ROM, used when coreboot fails to locate or validate a resource that is stored in ROM. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: Ie6de6590595d8fcdc57ad156237fffa03d5ead38 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-21src/arch/arm64: Remove variable set but not usedElyes HAOUAS
Change-Id: I4fe5771dd1ebf3d2a981dab08e98f1c018d14133 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-18SMBIOS: Fix SPD manufacture ID decoderLijian Zhao
According to JEP106 from JEDEC, fix manufacture ID of Crucial, Super Talnet and Micron. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I10a268a7f3bde405b95bd3a16d5d121be623c7ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/32837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-16{arch,cpu}/x86, drivers/intel: Restore cpu_index error handlingJacob Garber
Previously cpu_index() always succeeded, but since commit 095c931 (src/arch/x86: Use core apic id to get cpu_index()) it is now possible for it to indicate an error by returning -1. This commit adds error handling for all calls to cpu_index(), and restores several checks that were removed in commit 7c712bb (Fix code that would trip -Wtype-limits) but are now needed. Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I5436eed4cb5675f916924eb9670db04592a8b927 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-05-14Remove unnecessary ENV_RAMSTAGE guardSubrata Banik
TEST=Able to build coreboot for CML. Change-Id: Ic0f473e04ffc1de50dee871af52eacf0b328b376 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32764 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-13src/arch/x86: Use core apic id to get cpu_index()Subrata Banik
This cpu_index() implementation assumes that cpu_index() function might always getting called from coreboot context (ESP stack pointer will always refer to coreboot). This might not be true in case of proposed PI spec MP_SERVICES_PPI implementation, where FSP context (stack pointer refers to fsp) will request to get cpu_index(), natural alignment logic will use ESP and retrieve struct cpu_info *ci from (stack_top - 8 byte). This is not the place where cpu_index is actually stored by ramstage c_start.S Hence this patch tries to remove those dependencies while retrieving cpu_index(), rather it uses cpuid to fetch lapic id and matches with cpus_default_apic_id[] variable to return correct cpu_index(). BRANCH=none BUG=b:79562868 TEST=Ensures functions can be run on APs without any failure and cpu_index() also provides correct index number. Change-Id: I55023a3e0cf42f0496d45bc6af8ead447f402350 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26346 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-12nb/intel/snb: Drop NORTHBRIDGE_INTEL_IVYBRIDGENico Huber
We keep the support, though. Just now that `libgfxinit` is fixed, we don't need the distinction anymore. Causally, we also don't need CPU_INTEL_MODEL_306AX any more. TEST=Played tint on kontron/ktqm77. Score 606 Change-Id: Id1e33c77f44a66baacba375cbb2aeb71effb7b76 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-05-12arch/cpu: Rename mp_get_apic_id() and add_cpu_map_entry() functionSubrata Banik
This patch renames mp_get_apic_id() to cpu_get_apic_id() and add_cpu_map_entry() to cpu_add_map_entry() in order access it outside CONFIG_PARALLEL_MP kconfig scope. Also make below changes - Make cpu_add_map_entry() function available externally to call it from mp_init.c and lapic_cpu_init.c. BRANCH=none BUG=b:79562868 Change-Id: I6a6c85df055bc0b5fc8c850cfa04d50859067088 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-07smbios: Walk over PCI devicetree to fill type 9Patrick Rudolph
Use the devicetree values for type 9 slots. Tested on Lenovo T520. Change-Id: I1961d8af2d21f755ff52ad58804ea9b31d2a5b9b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-05-06arch/x86: Remove unused filePatrick Rudolph
The file is no longer used by any code. Remove it. Change-Id: I73f06cac11201dc37218d352ab995cf4f012c36a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-05-01arch/x86/acpi: Update VT-d DMA remapping structure flags settingJohn Zhao
DMA remapping structure flags settings are Bit 0: INTR_REMAP, Bit 1: X2APIC_OPT_OUT, Bit 2: DMA_CTRL_PLATFORM_OPT_IN_FLAG, Bits 3-7: Reserved (0). BUG=b:130351429 TEST=Image built and kernel booted to kernel. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Iaf4764a9062756cadc335d1932b0da8628797f5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/32516 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-26ACPI: Add RHSA and ANDD structures for DMAR tableJohn Zhao
Remapping Hardware Status Affinity (RHSA) structure is applicable for platforms supporting non-uniform memory. An ACPI Name-space Device Declaration (ANDD) structure uniquely represents an ACPI name-space enumerated device capable of issuing DMA requests in the platform. Add RHSA and ANDD structures support for DMAR table generation. BUG=b:130351429 TEST=Image built and booted to kernel Change-Id: I042925a7c03831061870d9bca03f11bf25aeb3e7 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-26x86/acpi: Add Kconfig to toggle 8259 reportingNico Huber
Change-Id: If3c9783ebc41c103c915788139d91644b805f397 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-04-23arch/x86/car.ld: Make the vboot tpm log symbols conditionalArthur Heymans
Without VBOOT_MEASURED_BOOT there is no need for these symbols. Change-Id: I96391b7817c79f760713c67bc469164b5514879e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-23smbios: Add memory type 9 system slot supportLijian Zhao
Add SMBIOS type 9 system slots into coreboot, the definiation is up to date with SMBIOS spec 3.2 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ibcfa377c260083203c1daf5562e103001f76b257 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-23ACPI: Clarify serial bus revision and specific revisionElyes HAOUAS
Serial bus revision [Byte 3] and serial bus specific revision [Byte 9] are not the same. Change-Id: I366f62e6aa0e9c0dfbc1ec17adeebc42a0e777eb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-04-23src: include <assert.h> when appropriateElyes HAOUAS
Change-Id: Ib843eb7144b7dc2932931b9e8f3f1d816bcc1e1a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Guckian
2019-04-23src: Use include <console/console.h> when appropriateElyes HAOUAS
Change-Id: Iddba5b03fc554a6edc4b26458d834e47958a6b08 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
2019-04-23src: Add missing include 'console.h'Elyes HAOUAS
Change-Id: Ie21c390ab04adb5b05d5f9760d227d2a175ccb56 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-04-22arch/x86/car.ld: Also check mrc.bin heap for IvybridgeArthur Heymans
Sandy- and ivybridge use the same mrc.bin that has the heap in an awkward location. Change-Id: If985a48c6703c8a86d8051e67595cf0fd409d99a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-19smbios: Fix copy paste errorPatrick Rudolph
As reported by Coverity Scan CID 1400679. Change-Id: I526b78a0697b7eb3c3dc75974c3a3a714b3d343f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32313 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-19smbios: Add type 17 device/bank locator overrideLijian Zhao
Current SMBIOS type 17 device and bank locator string is like "Channel-x-Dimm-x" and "Bank-x", x is deciminal number. Give silicon or mainboard vendor a chance to replace with something matches with silkscreen. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I54f7282244cb25a05780a3cdb9d1f5405c600513 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-19acpi: Upgrade acpi generate headerLijian Zhao
Sync acpigen.h content to match with laetst acpica, the link is https://github.com/acpica/acpica/blob/master/source/include/amlcode.h, and revision is 20190405. The purspose of the change is just make spec up to date. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: If5f5da70eb66472ddf5df0d72ca85de41faac128 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-17soc/intel/common/timer: Calculate TSC frequency based on CPUID 0x15Subrata Banik
This patch ensures to follow Intel SDM Vol 3B Sec 18.7.3 to calculate nominal TSC frequency. As per SDM recommendation: For any processor in which CPUID.15H is enumerated and MSR_PLATFORM_INFO[15:8] (which gives the scalable bus frequency) is available, a more accurate frequency can be obtained by using CPUID.15H This patch also adds header file to capture Intel processor model number. BUG=b:129839774 TEST=Boot ICL platform and calculate TSC frequency using below methods 1. TSC freq calculated based on MSR 0xCE tsc: Detected 1600.000 MHz processor 2. TSC freq calculated based on CPUID 0x15 tsc: Detected 1612.800 MHz TSC Method 2 actually reduce ~25ms of boot performance time. Note: Method 2 is recommended from gen 6 processor onwards. Change-Id: I9ff4b9159a94e61b7e634bd6095f7cc6d7df87c7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-04-09arch/x86/smbios: Reference type 7Patrick Rudolph
Fill in the handle to cache entries of type 7 in the type 4 structure. Tested on Intel Sandy Bridge (Lenovo T520). All 3 caches are referenced. Change-Id: Idf876b0c21c65f72a945d26c5898074b140763f8 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 11:12:12 +0000