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2016-07-28skylake/mainboard: Define mainboard hook in bootblockSubrata Banik
Move mainboard post console init functionality (google_chrome_ec_init & early_gpio programming) from verstage to bootblock. Add chromeos-ec support in bootblock BUG=chrome-os-partner:55357 BRANCH=none TEST=Built and boot kunimitsu till POST code 0x34 Change-Id: I1b912985a0234d103dcf025b1a88094e639d197d Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/15786 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-25console/post: be explicit about conditional cmos_post_log() compilingAaron Durbin
The current code was using !__PRE_RAM__ as a proxy for ramstage conditional compilation. In the face of postcar stage not defining __PRE_RAM__ (because it's after RAM is up) these code paths can fail to compile with a __SIMPLE_DEVICE__ defined for the entire stage. Remedy the current situation by just compiling explicity for ramstage because that was the original intent. In the future, the __SIMPLE_DEVICE__ selection for postcar can also be re-evaluated. Change-Id: I0f887f1e45f0cf5c235ae5144eaa227921e7119b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14958 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-23arch/x86: introduce postcar stage/phaseAaron Durbin
Certain chipsets don't have a memory-mapped boot media so their code execution for stages prior to DRAM initialization is backed by SRAM or cache-as-ram. The postcar stage/phase handles the cache-as-ram situation where in order to tear down cache-as-ram one needs to be executing out of a backing store that isn't transient. By current definition, cache-as-ram is volatile and tearing it down leads to its contents disappearing. Therefore provide a shim layer, postcar, that's loaded into memory and executed which does 2 things: 1. Tears down cache-as-ram with a chipset helper function. 2. Loads and runs ramstage. Because those 2 things are executed out of ram there's no issue of the code's backing store while executing the code that tears down cache-as-ram. The current implementation makes no assumption regarding cacheability of the DRAM itself. If the chipset code wishes to cache DRAM for loading of the postcar stage/phase then it's also up to the chipset to handle any coherency issues pertaining to cache-as-ram destruction. Change-Id: Ia58efdadd0b48f20cfe7de2f49ab462306c3a19b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14140 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-05Kconfig: hide useless options on ARM.Vladimir Serbinenko
Those options have no effect or lead to compile error on ARM due to fundamental incompatibilities. Add proper "depends on" clauses to hide them. Change-Id: I860fbd331439c25efd8aa92023195fda3add2e2c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13904 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-22console: Add higher baud ratesLee Leahy
Enable baud rates of 230400, 460800 and 921600. Leave the default set to 115200. TEST=Build and run on Galileo at 921600. Change-Id: I8e3980f33665bc183b454cf97c68e297f1b0502c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13755 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-09console: Disable SQUELCH_EARLY_SMP if SMP is not selectedLee Leahy
Add a "depends on SMP" to the value SQUELCH_EARLY_SMP Kconfig value to disable its selection when SMP is not enabled. TEST=Build for Galileo Change-Id: Ia3aa1d2169ed793e1bb26538b74b12347453d5af Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13639 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG <wangfei.jimei@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-21console: Simplify bootblock console Kconfig selection logicAlexandru Gagniuc
Instead of depending BOOTBLOCK_CONSOLE on a set of architectures, allow the arch or platform to specify whether it can provide a C environment. This simplifies the selection logic. Change-Id: Ia3e41796d9aea197cee0a073acce63761823c3aa Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/12871 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-18console/: add missing license headersDamien Roth
These were copied from the linux kernel, so get the standard corboot GPL v2 header. Change-Id: I27ef3326cc42b7e005f94c8b4fd355012a89561d Signed-off-by: Damien Roth <yves.r.roth@gmail.com> Reviewed-on: https://review.coreboot.org/13023 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-15src/console: Add x86 romstage spinlock option and printk spinlock supportTimothy Pearson
This paves the way for AP printk spinlock on AMD platforms Change-Id: Ice42a0d3177736bf6e1bc601092e413601866f20 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/11958 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-08console: Allow ARM64 platforms to select bootblock consoleMartin Roth
Change-Id: I09943aafe29f6e7a2a878e7b6141661982dfc645 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12658 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-21console: Add help for serial IO port selectionMartin Roth
Add help and a comment about the serial IO port selection to give the user better feedback when a port index is selected. Change-Id: I4c1614be51aee0286308fbc5c24554e218120bf7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12487 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-20rules.h: Add ENV_STRING and use it in console_init()Ben Gardner
Move the #ifdef chain to set the stage name to rules.h. Change-Id: I577ddf2de4ef249a1a4ce627bb55608731a9f5ed Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: http://review.coreboot.org/12479 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-19x86: Add Kconfig to disable early bootblock postcodesMartin Roth
The Intel cave creek chipset needs to have port 80 routing configured before any post codes can be sent to port 80h. Sending post codes out before the routing is done will hang the system. This patch allows us to disable the first couple of post codes that go out before the routing can be configured. The Kconfig symbol is selected by the cave creek chipset (fsp_i89xx). Change-Id: I9bf41669ec32744f87a1ed2de011d31c72ea38da Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12422 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: York Yang <york.yang@intel.com>
2015-11-17src/console: Link die.c in bootblock without BOOTBLOCK_CONSOLEAlexandru Gagniuc
Without BOOTBLOCK_CONSOLE any call to die() fails due to die() symbol not being defined at link time. die() is not is dependent on the console backend, and can function without it (the prink gets no-oped). Change-Id: I6cecafb576c3b1e901f3927c777f6282174fb259 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/12356 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-07arm64: remove secmonAaron Durbin
It's been decided to only support ARM Trusted Firmware for any EL3 monitor. That means any SoC that requires PSCI needs to add its support for ATF otherwise multi-processor bring up won't work. Change-Id: Ic931dbf5eff8765f4964374910123a197148f0ff Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11897 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-14x86: add standalone verstage supportAaron Durbin
To support x86 verstage one needs a working buffer for vboot. That buffer resides in the cache-as-ram region which persists across verstage and romstage. The current assumption is that verstage brings cache-as-ram up and romstage tears cache-as-ram down. The timestamp, cbmem console, and the vboot work buffer are persistent through in both romstage and verstage. The vboot work buffer as well as the cbmem console are permanently destroyed once cache-as-ram is torn down. The timestamp region is migrated. When verstage is enabled the assumption is that _start is the romstage entry point. It's currently expected that the chipset provides the entry point to romstage when verstage is employed. Also, the car_var_*() APIs use direct access when in verstage since its expected verstage does not tear down cache-as-ram. Lastly, supporting files were added to verstage-y such that an x86 verstage will build and link. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados using separate verstage. Change-Id: I097aa0b92f3bb95275205a3fd8b21362c67b97aa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11822 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-05Add EM100 'hyper term' spi console support in ramstage & smmMartin Roth
The EM100Pro allows the debug console to be sent over the SPI bus. This is not yet working in romstage due to the use of static variables in the SPI driver code. It is also not working on chipsets that have SPI write buffers of less than 10 characters due to the 9 byte command/header length specified by the EM100 protocol. While this currently works only with the EM100, it seems like it would be useful on any logic analyzer with SPI debug - just filter on command bytes of 0x11. Change-Id: Icd42ccd96cab0a10a4e70f4b02ecf9de8169564b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11743 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-26consoles: remove unused infrastructureAaron Durbin
The __console attribute as well as linker binding was dropped at some point. Kill of the dead code and infrastructure. Change-Id: I15e1fb4468fffe2e148ec9ac8539dfd958551807 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10279 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-19arm64: Reorganize payload entry code and related KconfigsJulius Werner
Remove the secmon Kconfig guard from Makefiles that add to the secmon class since they are redundant (the class is simply not used when compiling without secmon) to improve readability/ease-of-use. [pg: taken out of the patch linked below] Change-Id: I2f0ad8a923ca32fcade748ac8ee50c23cf9bafb9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270783 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10241 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-15console: Bring back newline translationKyösti Mälkki
Change-Id: Ib42f4a9eeb48dfb1a04e332aeb8f83dc4c4eef91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10188 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-13verstage: provide support for serial consoleAaron Durbin
verstage previously lacked serial console support. Add the necessary objects and macro checks to allow verstage to include the serial console. Change-Id: Ibe911ad347cac0b089f5bc0d4263956f44f3d116 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10196 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-05-13console: enumerate all known stagesAaron Durbin
There are more stages than currently handled in the initial message from console_init(). Add support for those including an UNKNOWN catchall. Change-Id: I2374db590072bdca8ff35116e2ecb2ad6459b697 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10194 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-05console: rename do_vtxprintf to do_printk_va_list and use itAaron Durbin
The name is more consistent with what we have elsewhere, and the callsite didn't build at all (with vboot enabled) Change-Id: I3576f3b8f737d360f68b67b6ce1683199948776d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10096 Tested-by: build bot (Jenkins)
2015-04-27cbmem: add and use a function to dump console bufferVadim Bendebury
The new function can be compiled in only when serial console is disabled. When invoked, this function initializes the serial interface and dumps the contents of the CBMEM console buffer to serial output. BRANCH=none BUG=chromium:475347 TEST=compiled for different platforms with and without serial console enabled. No actual test of this function yet. Change-Id: Ia8d16649dc9d09798fa6970f2cfd893438e00dc5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a38a8254dd788ad188ba2509b9ae117d6f699579 Original-Change-Id: Ib85759a2727e31ba1ca21da7e6c346e434f83b52 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/265293 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9984 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-23cbmem_console: fix it for x86Aaron Durbin
The Kconfig options pertaining cbmem console in the preram environment no longer make sense with the linker script changes. Remove them and their usage within cbmem_console. Change-Id: Ibf61645ca2331e4851e748e4e7aa5059e1192ed7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9851 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-14Add console wrapper for UART driverVadim Bendebury
Coreboot is designed to have a single serial console at most, on top of that it may have a CBMEM (virtual) console. Matters are complicated by the fact that console interface is different between bootblock and later stages. A linker list of console driver descriptors is used to allow to determine the set and type of console drivers at compile time. Even though the upstream seems to have done away with this approach, which does not seem the best idea. As an alternative this patch introduces a common wrapper which different UART drivers can plug in into. The driver exports a single API which can be used both directly (in bootblock) and through the wrapper (in later stages). The existing drivers can be adjusted to fit this scheme one by one. The common UART driver API also aligns fine with the upstream approach. BUG=chrome-os-partner:27784 TEST=none yet Original-Change-Id: Id1fe73d29f2a3c722bd77180beebaedb9bf7d6a1 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196660 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 94a36ad79a96f83d283c0fd073b05f98ae48820c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id1fe73d29f2a3c722bd77180beebaedb9bf7d6a1 Reviewed-on: http://review.coreboot.org/7872 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-06New mechanism to define SRAM/memory map with automatic bounds checkingJulius Werner
This patch creates a new mechanism to define the static memory layout (primarily in SRAM) for a given board, superseding the brittle mass of Kconfigs that we were using before. The core part is a memlayout.ld file in the mainboard directory (although boards are expected to just include the SoC default in most cases), which is the primary linker script for all stages (though not rmodules for now). It uses preprocessor macros from <memlayout.h> to form a different valid linker script for all stages while looking like a declarative, boilerplate-free map of memory addresses to the programmer. Linker asserts will automatically guarantee that the defined regions cannot overlap. Stages are defined with a maximum size that will be enforced by the linker. The file serves to both define and document the memory layout, so that the documentation cannot go missing or out of date. The mechanism is implemented for all boards in the ARM, ARM64 and MIPS architectures, and should be extended onto all systems using SRAM in the future. The CAR/XIP environment on x86 has very different requirements and the layout is generally not as static, so it will stay like it is and be unaffected by this patch (save for aligning some symbol names for consistency and sharing the new common ramstage linker script include). BUG=None TEST=Booted normally and in recovery mode, checked suspend/resume and the CBMEM console on Falco, Blaze (both normal and vboot2), Pinky and Pit. Compiled Ryu, Storm and Urara, manually compared the disassemblies with ToT and looked for red flags. Change-Id: Ifd2276417f2036cbe9c056f17e42f051bcd20e81 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f1e2028e7ebceeb2d71ff366150a37564595e614 Original-Change-Id: I005506add4e8fcdb74db6d5e6cb2d4cb1bd3cda5 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213370 Reviewed-on: http://review.coreboot.org/9283 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-06global: Refactor get_option usageVarad Gautam
Restructure get_option() calls to avoid unnecessary return value checks by pre-assigning defaults to the options being retrieved. Change-Id: I9159afe149a8eeed0785d1efd6eee8420b88b8f4 Signed-off-by: Varad Gautam <varadgautam@gmail.com> Reviewed-on: http://review.coreboot.org/8631 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-04build system: rename __BOOT_BLOCK__ and __VER_STAGE__Patrick Georgi
Drop the inner underscore for consistency. Follows the commit stated below. Change-Id: I75cde6e2cd55d2c0fbb5a2d125c359d91e14cf6d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Based-on-Change-Id: I6a1f25f7077328a8b5201a79b18fc4c2e22d0b06 Based-on-Signed-off-by: Julius Werner <jwerner@chromium.org> Based-on-Reviewed-on: https://chromium-review.googlesource.com/219172 Reviewed-on: http://review.coreboot.org/9290 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-03-30Avoid 64bit math on MIPS platformsVadim Bendebury
Low level 64 bit division and modulo functions are not available for MIPS platforms, but are required by the printk formatter. Modify the code to avoid 64 bit math when building for MIPS. In case the user does print a value exceeding 2^32, send a few junk characters to the output to indicate a corrupted value printed. [pg: add the printed sequence to the comment, so git grep can find it] BRANCH=none BUG=none TEST=startup code on Urara properly prints CBFS address values which are passed as 64 bit integers. Change-Id: Ie777019cd8d55c53d5e816fbacfe79893c3d64c7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8347f914a9cceca017668f8387ba679c2c79e66d Original-Change-Id: I25b8a900b3ba4ec1da3446dcc5f03101d5cdb757 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232294 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9162 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-28arm64: Add support for secure monitorFurquan Shaikh
Secure monitor runs at EL3 and is responsible for jumping to the payload at specified EL and also to manage features like PSCI. Adding basic implementation of secure monitor as a rmodule. Currently, it just jumps to the the payload at current EL. Support for switching el and PSCI will be added as separate patches. CQ-DEPEND=CL:218300 BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles succesfully and secure monitor loads and runs payload on ryu Change-Id: If0f22299a9bad4e93311154e5546f5bae3f3395c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5e40a21115aeac1cc3c73922bdc3e42d4cdb7d34 Original-Change-Id: I86d5e93583afac141ff61475bd05c8c82d17d926 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214371 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9080 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-25console: Convert cbmem log line endings to UNIX standardTimothy Pearson
The cbmem console output retains usage of the CRLF line ending. Converting line endings to the standard UNIX LF avoids the need to use dos2unix before running analysis on log files. Change-Id: I74a04ee69836d82640c94f250465acb4d1ee1071 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8857 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-23console: Allow bootblock console on MIPSPaul Burton
In addition to ARM based systems, allow MIPS based systems to select bootblock console support. BUG=chrome-os-partner:31438 TEST=none yet Change-Id: I40e5d8b651102709118878a317f7e983a617f433 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1a41853273ef9ae716d5645379fcef79c5771b87 Original-Change-Id: I41f03ea8c8104ba2dd9f532b084696385d29636c Original-Signed-off-by: Paul Burton <paul.burton@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/207973 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/8769 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-10console/Kconfig: Enable CBMEM console by defaultPaul Menzel
Currently on AMD boards no romstage messages can be saved in CBMEM, so only messages from ramstage on will be stored in CBMEM. Other than that nothing changes. Enabling CBMEM console by default does not noticeably decrease boot time as the messages are directly written to CAR or RAM. The board status script under `util/board_status/` reads the coreboot messages from CBMEM, which are then uploaded to the board status repository. With CBMEM console disabled by default, currently no coreboot console messages are uploaded to the board status repository, although it is important to have those. Enabling CBMEM console by default improves this situation, so that for all boards at least ramstage messages are stored in the board status repository. Change-Id: I8d5a58c078325c43a0317bcfaafc722d039aab0b Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5350 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-03-10x86 cache-as-ram: Remove BROKEN_CAR_MIGRATE optionKyösti Mälkki
This was added to handle cases of Intel FSP platforms that had EARLY_CBMEM_INIT but could not migrate CAR variables to CBMEM. These boards were recently fixed. To support combination of EARLY_CBMEM_INIT without CAR migration was added maintenance effort with little benefits. You had no CBMEM console for romstage and the few timestamps you could store were circulated via PCI scratchpads or CMOS nvram. Change-Id: I5cffb7f2b14c45b67ee70cf48be4d7a4c9e5f761 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8636 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-10cbmem console: Allow the cbmem console on non-x86 systems again.Gabe Black
If it's not supported on a particular board, either the build will fail or checks within the cbmem console itself should detect the problem. There shouldn't be random memory corruption any more. BUG=None TEST=Built with CONSOLE_CBMEM enabled on nyan and saw that it was actually enabled. BRANCH=None Original-Change-Id: Id6c8c7675daafe07aa4878cfcf13faefe576e520 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193167 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 20b486443bfc2d93d72bbc9e496023a00ab9ab30) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I39fbcdff61f6d8f520f2e9d7612dee78e97898b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7748 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-04Add stage information to coreboot bannerStefan Reinauer
As a convenience, print the actual stage name when entering a stage. Also unify the banner between bootblock / romstage and ramstage. No reason for two different occurences. Instead of this: coreboot-4.0 Tue May 13 14:13:37 PDT 2014 starting... [..] coreboot-4.0 Tue May 13 14:13:37 PDT 2014 starting... [..] coreboot-4.0 Tue May 13 14:13:37 PDT 2014 booting... you will see this: coreboot-4.0 Tue May 13 14:13:37 PDT 2014 bootblock starting... [..] coreboot-4.0 Tue May 13 14:13:37 PDT 2014 romstage starting... [..] coreboot-4.0 Tue May 13 14:13:37 PDT 2014 ramstage starting... Roughly based on: https://chromium-review.googlesource.com/199671 Change-Id: Id5894535e0551d113c80e4ff0514287391be1bef Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/8578 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-27CBMEM console: Fix and enhance pre-RAM supportKyösti Mälkki
Use the value of CONSOLE_PRERAM_BUFFER_SIZE to determine if we can do CBMEM console in bootblock and romstage. Kconfig forces it to zero if _BASE is unset or we cannot do CAR migration on x86. Add CBMEM console to bootblock, except for x86. Only one of bootblock and romstage clears the pre-RAM buffer. To start with empty console log on S3 wakeup, ramstage now clears previous contents of CBMEM buffer if there was no pre-RAM buffer. Unify Kconfig variable naming. TODO: ARM configurations do not define PRERAM_BUFFER_BASE values. Change-Id: I70d82da629529dbfd7bc9491223abd703cbc0115 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7862 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-01-27vboot2: implement select_firmware for pre-romstage verificationDaisuke Nojiri
This patch has a basic structure of vboot2 integration. It supports only Nyans, which have bootblock architecture and romstage architecture are compatible from linker's perspective. TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze. BUG=None BRANCH=none Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I4bbd4d0452604943b376bef20ea8a258820810aa Original-Reviewed-on: https://chromium-review.googlesource.com/204522 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit a6bce0cbed34def60386f3d9aece59e739740c58) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I63ddfbf463c8a83120828ec8ab994f8146f90001 Reviewed-on: http://review.coreboot.org/8160 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-01-09misc: Drop print_ implementation from non-romcc boardsStefan Reinauer
Because we had no stack on romcc boards, we had a separate, not as powerful clone of printk: print_*. Back in the day, like more than half a decade ago, we migrated a lot of boards to printk, but we never cleaned up the existing code to be consistent. Instead, we worked around the problem with a very messy console.h (nowadays the mess is hidden in romstage_console.c and early_print.h) This patch cleans up the generic code pieces to use printk() on all non-ROMCC boards. Our two remaining ROMCC boards are fixed up in this commit: bifferos/bifferboard and dmp/vortex86ex. Change-Id: I16676eeabe5c892c8e3c9f3c0cd3bae2e8fd74b6 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/8115 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Andrew Wu <arw@dmp.com.tw> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-05ipq8064: prepare UART driver for use in corebootVadim Bendebury
These driver needs to be in src/lib, and the include file needs to be renamed to avoid collision with the top level uart.h. BUG=chrome-os-partner:27784 TEST=emerge-storm coreboot still works Original-Change-Id: Ie12f44e055bbef0eb8b1a3ffc8d6742e7a446942 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196393 (cherry picked from commit c5618fd418642f5b009582f5f6bc51f7c9d54bec) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5e25ae350ac5e71b47a0daef078b03cc5ac35401 Reviewed-on: http://review.coreboot.org/7270 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-01Add UCB RISCV support for architecture, soc, and emulation mainboard..Ronald G. Minnich
Works in the RISCV version of QEMU. Note that the lzmadecode is so unclean that it needs a lot of work. A cleanup is in progress. We decided in Prague to do this as one thing, because it forms a nice case study of the bare minimum you need to add to get a new architecture going in qemu. Change-Id: If5af15c3a70733d219973e0d032746f8ab027e4d Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/7584 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-11-30Replace hlt() loops with halt()Patrick Georgi
Change-Id: I8486e70615f4c404a342cb86963b5357a934c41d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7606 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-20Replace includes of build.h with version.hKyösti Mälkki
As build.h is an auto-generated file it was necessary to add it as an explicit prerequisite in the Makefiles. When this was forgotten abuild would sometimes fail with following error: fatal error: build.h: No such file or directory Fix this error by compiling version.c into all stages. Change-Id: I342f341077cc7496aed279b00baaa957aa2af0db Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7510 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-19console: Isolate console_init() for ROMCCKyösti Mälkki
Change-Id: I623643834fb1c6af166a851fec7e31447944f0b6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7509 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-12Copy u-boot sources as is and modify the tree to still buildVadim Bendebury
This patch brings in ipq806x source files from the vendor's u-boot tree as it was published in the 'cs_banana' release. The following files are being copied: arch/arm/cpu/armv7/ipq/clock.c => src/soc/qualcomm/ipq806x/clock.c arch/arm/cpu/armv7/ipq/gpio.c => src/soc/qualcomm/ipq806x/gpio.c arch/arm/cpu/armv7/ipq/timer.c => src/soc/qualcomm/ipq806x/timer.c arch/arm/include/asm/arch-ipq806x/clock.h => src/soc/qualcomm/ipq806x/clock.h arch/arm/include/asm/arch-ipq806x/gpio.h => src/soc/qualcomm/ipq806x/gpio.h arch/arm/include/asm/arch-ipq806x/gsbi.h => src/soc/qualcomm/ipq806x/gsbi.h arch/arm/include/asm/arch-ipq806x/iomap.h => src/soc/qualcomm/ipq806x/iomap.h arch/arm/include/asm/arch-ipq806x/timer.h src/soc/qualcomm/ipq806x/timer.h arch/arm/include/asm/arch-ipq806x/uart.h => src/soc/qualcomm/ipq806x/uart.h board/qcom/ipq806x_cdp/ipq806x_cdp.c => src/mainboard/google/storm/cdp.c board/qcom/ipq806x_cdp/ipq806x_cdp.h => src/soc/qualcomm/ipq8064/cdp.h drivers/serial/ipq806x_uart.c => src/console/ipq806x_console.c Note that local timer.c gets overwritten with the original version. To prevent a build breakage some shortly to be reverted modifications had to be made to src/soc/qualcomm/ipq806x/Makefile.inc and src/soc/qualcomm/ipq806x/cbfs.c. BRANCH=none BUG=chrome-os-partner:27784 TEST='emerge-storm coreboot' still succeeds Original-Change-Id: I3f50bfbec2e18a3b5d2c640cff353a26f88c98c1 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/193722 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 3c9c2ede7e97e330cad2c2f3e557cc9bcdaecdcc) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia7bc66cecfc16f1dd4a9f3cb9840cbe91878adf4 Reviewed-on: http://review.coreboot.org/7263 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-10-07cbmem console: Locate the preram console with a symbol instead of a section.Gabe Black
On non-x86 systems, the location of the preram CBMEM console may not be in a predictable place relative to other things in the linker script. That makes it difficult to work with as its own section because the linker will complain if you try to move backwards as it lays out memory. If the console header is treated as an actual blob of memory which has to be put in the image, we'd have to predict where to put it so that it isn't before something with a lower address or after something with a higher address. Symbols, on the other hand, can be defined arbitrarily. Change-Id: I3257b981eee0c15bb997a9f2c55a03494c6ec6f0 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/193164 Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit a492761c27076bcac080013d509ae4aafd6dc3e3) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/7013 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-15arm: Remove CAR_MIGRATE Kconfig and associated cruftJulius Werner
This is essentially a revert of commit 10bd772d. The CAR_MIGRATE mechanism is only useful to migrate variables from a special region (e.g. cache as RAM) into DRAM-backed CBMEM between different parts of the romstage (it does not persist into ramstage). Since ARM devices use SRAM for which there is no reason to become inaccessible in later parts of the romstage, this mechanism isn't useful for them. Removing it makes the romstage.ld script much simpler, which has the nice side-effect of putting the BSS at the end of the memory image (so that cbfstool can actually figure out that it doesn't need to be part of the ROM image). Old-Change-Id: I50e91d8bd51b5deb19446d9da48699edecbef6ea Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176761 Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit ebfd698e57c902e2f39a0cfc1bc2b02665e47ec6) console: Make cbmem depend on x86. The cbmem implementation isn't supported on anything other than x86 right now and actually causes memory corruption on ARM machines. Until that's fixed, this will prevent people from turning it on and causing hard to track down errors. Old-Change-Id: I00e8aacf008acfe2f76d4eab82570f7c1cc89cab Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/191107 Reviewed-by: Julius Werner <jwerner@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit e54f16e346a7f2c66d802fb78a6b24e53b732b83) Squashed two related commits for cbmem support on arm. Change-Id: I2be48cea348ee5dc8ca3632d743500aa111bab08 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6888 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
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