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2018-04-28src/console: Add spaces around '=='Elyes HAOUAS
Change-Id: I61ff3adb573ffc99f37a1cdcbf5d0d83b2dec0ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25854 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-09console: Expose vsnprintfDavid Hendricks
It's a standard function. Change-Id: I039cce2dfc4e168804eb7d12b76a29af712ac7a1 Signed-off-by: David Hendricks <dhendricks@fb.com> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/23616 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-02console: only allow console messages after initializationAaron Durbin
The console subsystem allows printk() to be called prior to the drivers and/or infrastructure is completely set up. In those situations don't allow messages to be added until the console is completely initialized. BUG=b:73898539 Change-Id: Idc3840132d7f95f8e22045d7484c528d828bb0de Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/24917 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-23console: Introduce a way for mainboard to override the loglevelJulien Viard de Galbert
This change adds a config option to allow mainboard to override the console loglevel. When the option is set, the platform has to define the function get_console_loglevel returning a valid loglevel value. This allows a mainboard to sample a GPIO to switch the loglevel value between different environments (qualification vs production) without re-flashing. Change-Id: Id6cc72b8fe5c4c50a6f83ce80e6440b078eec6e2 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-02-21driver/uart: Introduce a way for mainboard to override the baudrateJulien Viard de Galbert
The rationale is to allow the mainboard to override the default baudrate for instance by sampling GPIOs at boot. A new configuration option is available for mainboards to select this behaviour. It will then have to define the function get_uart_baudrate to return the computed baudrate. Change-Id: I970ee788bf90b9e1a8c6ccdc5eee8029d9af0ecc Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-25console: Ignore loglevel in nvram until ramstageKyösti Mälkki
Calling get_option() triggers printk's before consoles are ready. Skip the call since console_loglevel is const anyways for __PRE_RAM__. Change-Id: I4d444bee1394449ce096c0aa30dca56365290e31 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-14console: Add weak method to notify about deathPatrick Rudolph
Call weak method die_notify. The method should be overwritten in mainboard directory to signal that a fatal error had occurred. On boards that do share the same EC and where the EC is capable of controlling LEDs or a buzzer the method can be overwritten in EC directory instead. Tested on Lenovo T500. Change-Id: I71f8ddfc96047e8a0d39f084588db1fe2f251612 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19696 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-07-13src: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
These are places that were missed on the first pass. Change-Id: Ia6511f0325433ab020946078923bf7ad6f0362a3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20358 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-06-12src/console: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: I5a674cd7a360a0dd040c859ec1f8d760d7c83364 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-06-04console/flashsconsole: Add spi flash console for debuggingYouness Alaoui
If CONSOLE_SPI_FLASH config is enabled, we write the cbmem messages to the 'CONSOLE' area in FMAP which allows us to grab the log when we read the flash. This is useful when you don't have usb debugging, and UART lines are hard to find. Since a failure to boot would require a hardware flasher anyways, we can get the log at the same time. This feature should only be used when no alternative is found and only when we can't boot the system, because excessive writes to the flash is not recommended. This has been tested on purism/librem13 v2 and librem 15 v3 which run Intel Skylake hardware. It has not been tested on other archs or with a driver other than the fast_spi. Change-Id: I74a297b94f6881d8c27cbe5168f161d8331c3df3 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/19849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-18cbmem_console: Improve 'cbmem -1' behavior for truncated pre-CBMEM logsJulius Werner
The 'cbmem -1' flag that cuts off console output before the last boot will ignore content from earlier stages if it was truncated due to lack of pre-CBMEM console space. This patch makes the "log truncated" message more specific and adds it as an additional cut-off marker to 'cbmem -1' to counteract that problem. Also raise the log level of the coreboot banner one step to BIOS_NOTICE to make it more likely to be included in the output for 'cbmem -1' to find. (I believe NOTICE is reasonable but I wouldn't want to go as far as WARN which should be reserved for actual problems. Of course this is not ideal, but then again, our whole log-level system really isn't... it would be better if we could make it always print a banner to the CBMEM console without affecting the UART at the same time, but that would require a larger amount of work.) Change-Id: I58288593dfa757e14f4a9da4ffa7e27b0b66feb9 Reported-by: https://ticket.coreboot.org/issues/117 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-25console: rework log level to not be reliant on ROMSTAGE_CONSTAaron Durbin
The console log level variable doesn't really rely on ROMSTAGE_CONST proper. Instead, the mutability of the variable is based on the current implementation of ROMSTAGE_CONST (__PRE_RAM__). As such directly use that logic for the code. In addition, refactor the code to let the compiler and linker optimize out accesses instead of using the pre-processor. Change-Id: I44bcc409266ef52b9be29f75efde73a6707a53f4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19438 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-04-24console: Make snprintf available in all stagesPaul Menzel
Change-Id: If5e255c75e7774393ef7e4febef84d97a1a3a118 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/19366 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2016-12-27console: Enable do_printk_va_list for VBOOTLee Leahy
Use CONFIG_VBOOT to enable do_printk_va_list to match the conditionals in include/console/console.h and the only caller is vboot/vboot_logic.c. CONFIG_VBOOT is also selected for CONFIG_CHROMEOS. TEST=Build and run on Galileo Gen2 Change-Id: Ia115c74afa498a14d5edd6f7940ec2edc124516f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/17967 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-29Hook up libhwbase in ramstageNico Huber
It's hidden behind a configuration option `CONFIG_RAMSTAGE_LIBHWBASE`. This also adds some glue code to use the coreboot console for debug output and our monotonic timer framework as timer backend. v2: Also update 3rdparty/libhwbase to the latest master commit. Change-Id: I8e8d50271b46aac1141f95ab55ad323ac0889a8d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16951 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-11-21console/vtxprintf.c: cast precision to size_t for string lengthMartin Roth
If no maximum string length is specified, we're intentionally passing a value of -1 to get the string length so that it's not limited. This makes checking tools unhappy, so actively cast it to size_t before passing it into strlen to show that it's not an accident. Addresses coverity issue 1129133 - Argument cannot be negative Change-Id: I40f8f2101e170a5c96fcd39c217aa414f4316473 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17479 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-18Revert "[WIP] console/Kconfig: Calculate COM port base addresses only on x86"Ronald G. Minnich
This reverts commit 2c8f3bd91b54e85b4d2e24894ee8bbbfb9ad8a31. I mistakenly commited a WIP, sorry. Change-Id: I3c66c688dbfd903ecf5303abcdf6b5ded84585c7 Reviewed-on: https://review.coreboot.org/17028 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-15[WIP] console/Kconfig: Calculate COM port base addresses only on x86Jonathan Neuschäfer
On other architectures, the serial ports aren't mapped at 0x3f8. WIP: I'm not sure how exactly the dependency should be encoded in Kconfig. Change-Id: Ia1de545325a53607f62d08e76b2f61b25edbe6ef Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16982 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-10-02Kconfig: Update default hex values to start with 0xMartin Roth
Kconfig hex values don't need to be in quotes, and should start with '0x'. If the default value isn't set this way, Kconfig will add the 0x to the start, and the entry can be added unnecessarily to the defconfig since it's "different" than what was set by the default. A check for this has been added to the Kconfig lint tool. Change-Id: I86f37340682771700011b6285e4b4af41b7e9968 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16834 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-09-19console: honor CONFIG_POSTCAR_CONSOLEAaron Durbin
The declarations for console_init() were unconditionally exposed even though there is a Kconfig option. Correct this by honoring the CONFIG_POSTCAR_CONSOLE condition. BUG=chrome-os-partner:57513 Change-Id: Id45ae3d7c05a9f4ebcf85c446fc68a709513bb0f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16617 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-31src/console: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: Ibb2ce383322c174bdb3bcc88ae35c17f179f6d21 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16323 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-10console: Add write line routineLee Leahy
Add write line routine which is called indirectly by FSP. TEST=Build and run on Galileo Gen2. Change-Id: Idefb6e9ebe5a2b614055dabddc1882bfa3bba673 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16127 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-01arch/x86: Enable postcar consoleLee Leahy
Add a Kconfig value to enable the console during postcar. Add a call to console_init at the beginning of the postcar stage in exit_car.S. TEST=Build and run on Galileo Gen2 Change-Id: I66e2ec83344129ede2c7d6e5627c8062e28f50ad Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16001 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-28skylake/mainboard: Define mainboard hook in bootblockSubrata Banik
Move mainboard post console init functionality (google_chrome_ec_init & early_gpio programming) from verstage to bootblock. Add chromeos-ec support in bootblock BUG=chrome-os-partner:55357 BRANCH=none TEST=Built and boot kunimitsu till POST code 0x34 Change-Id: I1b912985a0234d103dcf025b1a88094e639d197d Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/15786 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-25console/post: be explicit about conditional cmos_post_log() compilingAaron Durbin
The current code was using !__PRE_RAM__ as a proxy for ramstage conditional compilation. In the face of postcar stage not defining __PRE_RAM__ (because it's after RAM is up) these code paths can fail to compile with a __SIMPLE_DEVICE__ defined for the entire stage. Remedy the current situation by just compiling explicity for ramstage because that was the original intent. In the future, the __SIMPLE_DEVICE__ selection for postcar can also be re-evaluated. Change-Id: I0f887f1e45f0cf5c235ae5144eaa227921e7119b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14958 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-23arch/x86: introduce postcar stage/phaseAaron Durbin
Certain chipsets don't have a memory-mapped boot media so their code execution for stages prior to DRAM initialization is backed by SRAM or cache-as-ram. The postcar stage/phase handles the cache-as-ram situation where in order to tear down cache-as-ram one needs to be executing out of a backing store that isn't transient. By current definition, cache-as-ram is volatile and tearing it down leads to its contents disappearing. Therefore provide a shim layer, postcar, that's loaded into memory and executed which does 2 things: 1. Tears down cache-as-ram with a chipset helper function. 2. Loads and runs ramstage. Because those 2 things are executed out of ram there's no issue of the code's backing store while executing the code that tears down cache-as-ram. The current implementation makes no assumption regarding cacheability of the DRAM itself. If the chipset code wishes to cache DRAM for loading of the postcar stage/phase then it's also up to the chipset to handle any coherency issues pertaining to cache-as-ram destruction. Change-Id: Ia58efdadd0b48f20cfe7de2f49ab462306c3a19b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14140 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-05Kconfig: hide useless options on ARM.Vladimir Serbinenko
Those options have no effect or lead to compile error on ARM due to fundamental incompatibilities. Add proper "depends on" clauses to hide them. Change-Id: I860fbd331439c25efd8aa92023195fda3add2e2c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13904 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-22console: Add higher baud ratesLee Leahy
Enable baud rates of 230400, 460800 and 921600. Leave the default set to 115200. TEST=Build and run on Galileo at 921600. Change-Id: I8e3980f33665bc183b454cf97c68e297f1b0502c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13755 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-09console: Disable SQUELCH_EARLY_SMP if SMP is not selectedLee Leahy
Add a "depends on SMP" to the value SQUELCH_EARLY_SMP Kconfig value to disable its selection when SMP is not enabled. TEST=Build for Galileo Change-Id: Ia3aa1d2169ed793e1bb26538b74b12347453d5af Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13639 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG <wangfei.jimei@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-21console: Simplify bootblock console Kconfig selection logicAlexandru Gagniuc
Instead of depending BOOTBLOCK_CONSOLE on a set of architectures, allow the arch or platform to specify whether it can provide a C environment. This simplifies the selection logic. Change-Id: Ia3e41796d9aea197cee0a073acce63761823c3aa Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/12871 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-18console/: add missing license headersDamien Roth
These were copied from the linux kernel, so get the standard corboot GPL v2 header. Change-Id: I27ef3326cc42b7e005f94c8b4fd355012a89561d Signed-off-by: Damien Roth <yves.r.roth@gmail.com> Reviewed-on: https://review.coreboot.org/13023 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-15src/console: Add x86 romstage spinlock option and printk spinlock supportTimothy Pearson
This paves the way for AP printk spinlock on AMD platforms Change-Id: Ice42a0d3177736bf6e1bc601092e413601866f20 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/11958 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-08console: Allow ARM64 platforms to select bootblock consoleMartin Roth
Change-Id: I09943aafe29f6e7a2a878e7b6141661982dfc645 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12658 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-21console: Add help for serial IO port selectionMartin Roth
Add help and a comment about the serial IO port selection to give the user better feedback when a port index is selected. Change-Id: I4c1614be51aee0286308fbc5c24554e218120bf7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12487 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-20rules.h: Add ENV_STRING and use it in console_init()Ben Gardner
Move the #ifdef chain to set the stage name to rules.h. Change-Id: I577ddf2de4ef249a1a4ce627bb55608731a9f5ed Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: http://review.coreboot.org/12479 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-19x86: Add Kconfig to disable early bootblock postcodesMartin Roth
The Intel cave creek chipset needs to have port 80 routing configured before any post codes can be sent to port 80h. Sending post codes out before the routing is done will hang the system. This patch allows us to disable the first couple of post codes that go out before the routing can be configured. The Kconfig symbol is selected by the cave creek chipset (fsp_i89xx). Change-Id: I9bf41669ec32744f87a1ed2de011d31c72ea38da Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12422 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: York Yang <york.yang@intel.com>
2015-11-17src/console: Link die.c in bootblock without BOOTBLOCK_CONSOLEAlexandru Gagniuc
Without BOOTBLOCK_CONSOLE any call to die() fails due to die() symbol not being defined at link time. die() is not is dependent on the console backend, and can function without it (the prink gets no-oped). Change-Id: I6cecafb576c3b1e901f3927c777f6282174fb259 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/12356 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-07arm64: remove secmonAaron Durbin
It's been decided to only support ARM Trusted Firmware for any EL3 monitor. That means any SoC that requires PSCI needs to add its support for ATF otherwise multi-processor bring up won't work. Change-Id: Ic931dbf5eff8765f4964374910123a197148f0ff Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11897 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-14x86: add standalone verstage supportAaron Durbin
To support x86 verstage one needs a working buffer for vboot. That buffer resides in the cache-as-ram region which persists across verstage and romstage. The current assumption is that verstage brings cache-as-ram up and romstage tears cache-as-ram down. The timestamp, cbmem console, and the vboot work buffer are persistent through in both romstage and verstage. The vboot work buffer as well as the cbmem console are permanently destroyed once cache-as-ram is torn down. The timestamp region is migrated. When verstage is enabled the assumption is that _start is the romstage entry point. It's currently expected that the chipset provides the entry point to romstage when verstage is employed. Also, the car_var_*() APIs use direct access when in verstage since its expected verstage does not tear down cache-as-ram. Lastly, supporting files were added to verstage-y such that an x86 verstage will build and link. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados using separate verstage. Change-Id: I097aa0b92f3bb95275205a3fd8b21362c67b97aa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11822 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-05Add EM100 'hyper term' spi console support in ramstage & smmMartin Roth
The EM100Pro allows the debug console to be sent over the SPI bus. This is not yet working in romstage due to the use of static variables in the SPI driver code. It is also not working on chipsets that have SPI write buffers of less than 10 characters due to the 9 byte command/header length specified by the EM100 protocol. While this currently works only with the EM100, it seems like it would be useful on any logic analyzer with SPI debug - just filter on command bytes of 0x11. Change-Id: Icd42ccd96cab0a10a4e70f4b02ecf9de8169564b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11743 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-26consoles: remove unused infrastructureAaron Durbin
The __console attribute as well as linker binding was dropped at some point. Kill of the dead code and infrastructure. Change-Id: I15e1fb4468fffe2e148ec9ac8539dfd958551807 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10279 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-19arm64: Reorganize payload entry code and related KconfigsJulius Werner
Remove the secmon Kconfig guard from Makefiles that add to the secmon class since they are redundant (the class is simply not used when compiling without secmon) to improve readability/ease-of-use. [pg: taken out of the patch linked below] Change-Id: I2f0ad8a923ca32fcade748ac8ee50c23cf9bafb9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270783 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10241 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-15console: Bring back newline translationKyösti Mälkki
Change-Id: Ib42f4a9eeb48dfb1a04e332aeb8f83dc4c4eef91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10188 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-13verstage: provide support for serial consoleAaron Durbin
verstage previously lacked serial console support. Add the necessary objects and macro checks to allow verstage to include the serial console. Change-Id: Ibe911ad347cac0b089f5bc0d4263956f44f3d116 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10196 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-05-13console: enumerate all known stagesAaron Durbin
There are more stages than currently handled in the initial message from console_init(). Add support for those including an UNKNOWN catchall. Change-Id: I2374db590072bdca8ff35116e2ecb2ad6459b697 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10194 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-05console: rename do_vtxprintf to do_printk_va_list and use itAaron Durbin
The name is more consistent with what we have elsewhere, and the callsite didn't build at all (with vboot enabled) Change-Id: I3576f3b8f737d360f68b67b6ce1683199948776d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10096 Tested-by: build bot (Jenkins)
2015-04-27cbmem: add and use a function to dump console bufferVadim Bendebury
The new function can be compiled in only when serial console is disabled. When invoked, this function initializes the serial interface and dumps the contents of the CBMEM console buffer to serial output. BRANCH=none BUG=chromium:475347 TEST=compiled for different platforms with and without serial console enabled. No actual test of this function yet. Change-Id: Ia8d16649dc9d09798fa6970f2cfd893438e00dc5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a38a8254dd788ad188ba2509b9ae117d6f699579 Original-Change-Id: Ib85759a2727e31ba1ca21da7e6c346e434f83b52 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/265293 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9984 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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