coreboot - Some coreboot project code with my work

Age	Commit message (Collapse)	Author
2015-03-18	bootstate: use structure pointers for scheduling callbacks	Aaron Durbin
	The GCC 4.9.2 update showed that the boot_state_init_entry structures were being padded and assumed to be aligned in to an increased size. The bootstate scheduler for static entries, boot_state_schedule_static_entries(), was then calculating the wrong values within the array. To fix this just use a pointer to the boot_state_init_entry structure that needs to be scheduled. In addition to the previous issue noted above, the .bs_init section was sitting in the read only portion of the image while the fields within it need to be writable. Also, the boot_state_schedule_static_entries() was using symbol comparison to terminate a loop which in C can lead the compiler to always evaluate the loop at least once since the language spec indicates no 2 symbols can be the same value. Change-Id: I6dc5331c2979d508dde3cd5c3332903d40d8048b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8699 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-16	cpu/amd/pi: Add amd_initcpuio() and amd_initmmio()	Dave Frodin
	This makes the change to the cpu/amd/pi/00730F01 that was made for the cpu/amd/agesa based boards in: commit 48518f0d AGESA: Add amd_initcpuio() and amd_initmmio() These are not wrappers for AGESA as they do not enter vendorcode at all. We expect most of the added fixme.c file to be written without use of AMDLIB.h and parts relocated as northbridge enable_resources(). The equivalent change has already been made for cpu/amd/pi/00630F01. Change-Id: I591b50ee807436f5a1dee14d2c88a77462024744 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8670 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-10	x86 cache-as-ram: Remove BROKEN_CAR_MIGRATE option	Kyösti Mälkki
	This was added to handle cases of Intel FSP platforms that had EARLY_CBMEM_INIT but could not migrate CAR variables to CBMEM. These boards were recently fixed. To support combination of EARLY_CBMEM_INIT without CAR migration was added maintenance effort with little benefits. You had no CBMEM console for romstage and the few timestamps you could store were circulated via PCI scratchpads or CMOS nvram. Change-Id: I5cffb7f2b14c45b67ee70cf48be4d7a4c9e5f761 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8636 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-21	cpu/amd/pi: Use alloc_cbmem() only in ramstage	Dave Frodin
	Without this change the builder would fail with the complaint that there was a global static variable in romstage. alloc_cbmem() is only called in ramstage. The alternative was to add /cpu/amd/pi/.romstage.o to the list of illegal_globals EXCLUDE_FILEs in arch/x86/init/romstage.ld. TEST: Booted the amd/lamar board. Change-Id: I5167910ff790a3152a4ad8e5af0a4a3b17894f0f Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8256 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-21	AMD Bald Eagle: Add CPU subdirectory files for new AMD processor	Bruce Griffith
	This adds the AMD Family 15h model 30 CPU. S3 suspend/resume currently is not supported. Tested on the amd/lamar platform. Change-Id: Ifef55747a5d715b17937fc75ab9d35945b59f0e6 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/7248 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-18	amd/00730F01: Move SteppeEagle specific settings to northbridge	Dave Frodin
	These settings are specific to the SteppeEagle SOC and should be made in its northbridge code rather than the CPU code. Change-Id: I1a231f95225e1414b0cbc026a2a7b7797bd91fca Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8254 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-27	vboot2: add verstage	Stefan Reinauer
	This reverts the revert commit 5780d6f3876723b94fbe3653c9d87dad6330862e and fixes the build issue that cuased it to be reverted. Verstage will host vboot2 for firmware verification. It's a stage in the sense that it has its own set of toolchains, compiler flags, and includes. This allows us to easily add object files as needed. But it's directly linked to bootblock. This allows us to avoid code duplication for stage loading and jumping (e.g. cbfs driver) for the boards where bootblock has to run in a different architecture (e.g. Tegra124). To avoid name space conflict, verstage symbols are prefixed with verstage_. TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze. BUG=None BRANCH=none Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Iad57741157ec70426c676e46c5855e6797ac1dac Original-Reviewed-on: https://chromium-review.googlesource.com/204376 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit 27940f891678dae975b68f2fc729ad7348192af3) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I2a83b87c29d98d97ae316091cf3ed7b024e21daf Reviewed-on: http://review.coreboot.org/8224 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09	cpu/amd/pi: Use acpi_is_wakeup()	Kyösti Mälkki
	Propagate commit 9107e53 from amd/agesa and fix some related #includes under cpu/amd/pi. Change test to return true on S2 wakeup too. In S2 CPU would have been powered down so MTRR recovery is required. Change-Id: I18cb31c1124da53e5fcba2610f6b02d755feb092 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8171 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-19	AMD binaryPI: Drop EXT_CONF_SUPPORT	Kyösti Mälkki
	Change-Id: I2ec08df2eb8e65bc759de9917894df9d0c8b1995 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7807 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-20	amd/olivehillplus: Share agesawrapper header	Kyösti Mälkki
	This interface is common with AMD PI implementations. Change-Id: Ifabfce97db749e04aa19e53f62216be78158b282 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7150 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Tested-by: build bot (Jenkins)
2014-11-20	AMD: Isolate AGESA and PI build environments	Kyösti Mälkki
	To backport features introduced with recent Chromebooks and/or Intel boards in general, heavy work on the AMD AGESA platform infrastructure is required. With the AGESA PI available in binary form only, community members have little means to verify, debug and develop for the said platforms. Thus it makes sense to fork the existing agesawrapper interfaces, to give AMD PI platforms a clean and independent sandbox. New directory layout reflects the separation already taken place under 3rdparty/ and vendorcode/. Change-Id: Ib60861266f8a70666617dde811663f2d5891a9e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7149 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Tested-by: build bot (Jenkins)