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2019-01-14binaryPI: Drop CONFIG_CBB and CONFIG_CDBKyösti Mälkki
Static values, copy paste from multi-node fam15 code. Add header that shall have declarations of functions common to different families factored out. Change-Id: I2401acb9269674bac054fa9a6dd60ca8a21b36a9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-10binaryPI: Drop warning on EXT_CONF_SUPPORTKyösti Mälkki
Copy-paste from fam15 code. Change-Id: Ic52031c57a8b659bff5ca03a66ec2291140d2233 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-18cpu: Remove unneeded include <pc80/mc146818rtc.h>Elyes HAOUAS
Change-Id: I67bc60b9e0eb6289193d698787c18ea4593c991a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-11-16amd/{nb/amdfam10,cpu/pi}/Kconfig: Remove unused symbolsElyes HAOUAS
Change-Id: I7019d70b7e6f8ae041a12d6bab83127e9e70868c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16src: Remove unneeded include <console/console.h>Elyes HAOUAS
Change-Id: I40f8b4c7cbc55e16929b1f40d18bb5a9c19845da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-10-30{cpu,drivers,nb,sb}/amd: Replace {MSR,MTRR} addresses with macrosElyes HAOUAS
Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29243 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-19{cpu,drivers}/amd: Replace MTRR addresses with macrosElyes HAOUAS
Change-Id: I315c0b70c552c5dd7f640b18b913350bb88be81b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29173 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18cpu/amd: Use common AMD's MSRElyes HAOUAS
Phase 1. Due to the size of the effort, this CL is broken into several phases. Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-08-08cpu/amd: Correct number of MCA banks clearedMarshall Dawson
Use the value discovered in the MCG_CAP[Count] for the number of MCA status registers to clear. The generations should have the following number of banks: * Family 10h: 6 banks * Family 12h: 6 * Family 14h: 6 * Family 15h: 7 * Family 16h: 6 Change-Id: I0fc6d127a200b10fd484e051d84353cc61b27a41 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08cpu/amd: Improve formattingMarshall Dawson
Remove for() braces from around single lines. Remove extra blank lines. This cleans up checkpatch problems in a subsequent patch. Change-Id: I329ac03365e51799581c56eed27ee54de6826f14 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08cpu/amd: Rename MCA status registerMarshall Dawson
Change the defined name of MCI_STATUS (i.e. MCi_STATUS) to reflect its MC0_STATUS address. Change-Id: I97d2631a186965bb8b18f544ed9648b3a71f5fb0 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-09src/{arch,commonlib,cpu}: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: I8e4118c5c5d70719ad7dc5f9ff9f86d93fa498ac Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-06-14cpu/amd: Remove duplicated includesElyes HAOUAS
Change-Id: I3544ce4a573b6996d64b140d8acdaeb3de430896 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-30cpu/amd: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: I4b930a191130941c8349861cdd803a5be4219274 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23653 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-23Constify struct cpu_device_id instancesJonathan Neuschäfer
There is currently no case where a struct cpu_device_id instance needs to be modified. Thus, declare all instances as const. Change-Id: I5ec7460b56d75d255b3451d76a46df76a51d6365 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16cpu/amd: Fix spelling of *implementation*Paul Menzel
Change-Id: I3ef810ee59492c8d7147934e61523c8fd223863b Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/22013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-02binaryPI: Fix boot regressionsKyösti Mälkki
Fix boot regression after commit d4955f0 AGESA: Move API interface under drivers/ Boards were left without cache-as-ram setup code and appeared completely dead. Change-Id: I53a58b817310e91566db3fd660a2c41556f3df5f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
2017-09-29AGESA binaryPI: Fix indirect AGESA.h includeKyösti Mälkki
Change-Id: I5e2affe337f7e61ca79530b3a77af963e8692ff1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-26AGESA: Move API interface under drivers/Kyösti Mälkki
New AGESA support files will be used for binaryPI platforms as well. Furthermore, some of those should move from split nb/ sb/ directories to soc/, so move support files for the API under drivers/. Change-Id: I549788091de91f61de8b9adc223d52ffb5732235 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26AGESA: Implement POSTCAR_STAGEKyösti Mälkki
Move all boards that have moved away from AGESA_LEGACY_WRAPPER or BINARYPI_LEGACY_WRAPPER to use POSTCAR_STAGE. We use POSTCAR_STAGE as a conditional in CAR teardown to tell our MTRR setup is prepared such that invalidation without writeback is a valid operation. Change-Id: I3f4e2170054bdb84c72d2f7c956f8d51a6d7f0ca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-10AGESA binaryPI: Remove heapmanager from romstageKyösti Mälkki
With AMD_INIT_ENV and AMD_INIT_S3LATERESTORE moved from romstage to ramstage, heapamanager in romstage is no longer needed. Change-Id: Iea8ad3ddb245c83dd290436ac9d4ecac9350b88c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06AGESA: Rename assembly from .inc to .SKyösti Mälkki
Change-Id: I5f90df92e0ac27e98edf23784eeec5618d150430 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-02binaryPI: Introduce BINARYPI_LEGACY_WRAPPER and its counterpartKyösti Mälkki
We define BINARYPI_LEGACY_WRAPPER a method of calling AGESA via functions in agesawrapper.c file. The approach implemented there makes it very inconvenient to do board-specific customisation or present common platform-specific features. Seems like it also causes assertion errors on AGESA side. The flag is applied here to all boards and then individually removed one at a time, as things get tested. New method is not to call AGESA internal functions directly, but via the dispatcher. AGESA call parameters are routed to hooks in both platform and board -directories, to allow for easy capture or modification as needed. For each AGESA dispatcher call made, eventlog entries are replayed to the console log. Also relocations of AGESA heap that took place are recorded. New method is expected to be compatible with binaryPI. Change-Id: I2900249e60f21a13dc231f4a8a04835e090109d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02binaryPI: Enable EARLY_CBMEM_INITKyösti Mälkki
Also moves postcar stack to CBMEM. Change-Id: I0263af9561e0367bbbde4d5c3190039f4c3047a0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19347 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-08-02AGESA binaryPI: Unify agesawrapper headerKyösti Mälkki
Change-Id: I54c8553bc057798e595b28f6cbc07f7125ae074f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-01cpu/amd/pi: Fix checkpatch warnings and errorsEvelyn Huang
Fix remaining space prohibited between function name and open parenthesis, line over 80 characters, unnecessary braces for single statement blocks, space required before open brace errors and warnings in subdirectories of src/cpu/amd/pi Change-Id: I177ffe98a3674bd700a39eb8073db34adf9499b4 Signed-off-by: Evelyn Huang <evhuang@google.com> Reviewed-on: https://review.coreboot.org/20098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-07-29binaryPI: Drop remains of ACPI S3 on FCHKyösti Mälkki
Never reached and actual code was already wiped out. Change-Id: Ic17cbc56e83d23e228e23578357843ac9cd77eda Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20623 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-17binaryPI: Disable CAR with empty stackKyösti Mälkki
Calling disable_cache_as_ram() with valuables in stack is not a stable solution, as per documentation AMD_DISABLE_STACK should destroy stack in cache. While we still preserve cache contents (there is wbinvd deep inside AMD_DISABLE_STACK macro), we now actually do a stack switch and much more closely meet the specification of CAR teardown sequence in AGESA specifications. We now somewhat incorrectly include files from agesa/ tree, but the whole agesawrapper.c file removal will address the issue of overall directory layout. Change-Id: I2bac098099c1caffea181356c63924f4b5a93b54 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-17binaryPI: Switch to agesa/heapmanager.cKyösti Mälkki
Essentially squashes following commits from AGESA side. 45ff9cb AGESA: Reduce typecasting in heapmanager calls bceccec AGESA: Handle HEAP_CALLOUT_RUNTIME allocation more cleanly 4240277 AGESA: Adjust heap location for S3 resume path 424c639 AGESA: Refactor S3 support functions 50e6daf AGESA: Log heap initialisation da74041 AGESA: Move heap allocator declarations c74b53f AGESA: Reduce SPI use by 24kB for S3 support b1fcbf3 AGESA: Separate HeapManager declarations from BiosCallOuts f728408 AGESA: Split S3 backup in CBMEM 82fbda7 AGESA: Use same HeapManager for all BiosCallOuts Change-Id: I537bd05a3e06ff6896f1ac8be93eed5321ca472b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-12binaryPI: Drop non-soc stoneyridge treesKyösti Mälkki
These sources are no longer part of build-tests and transition to soc/ appears to be completed. Change-Id: I9bc2212f44d79c795e5b8f6d62b6ee3c42de779a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-06-28cpu/amd: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: I9f4155285529ec28e826637a61436478f648704c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-28cpu/*: Add whitespace around '<<'Elyes HAOUAS
Change-Id: Id46c0b57bd7c9b954b29537c70254df947690e0b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-27vendorcode/amd: Unify Porting.h across all targetsStefan Reinauer
This requires to also unify the calling convention for AGESA functions from AGESA_STATUS (*agesa_func)(UINT32 Func, UINT32 Data, VOID *ConfigPtr) to AGESA_STATUS (*agesa_func)(UINT32 Func, UINTN Data, VOID *ConfigPtr) On systems running 32bit x86 code this will not make a difference as UINTN is uintptr_t which is 32bit on these machines. Change-Id: I095ec2273c18a9fda11712654e290ebc41b27bd9 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-06-12src/cpu/amd/pi/00630F01 Fix checkpatch warnings and errorsEvelyn Huang
Fix space prohibited between function name and open parenthesis, line over 80 characters, unnecessary braces for single statement blocks, space required before open brace errors and warnings Change-Id: I66f1a8640ec5c9d8a1dd039088598f40e8d30f95 Signed-off-by: Evelyn Huang <evhuang@google.com> Reviewed-on: https://review.coreboot.org/20096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-19drivers/spi/spi_flash: Pass in flash structure to fill in probeFurquan Shaikh
Instead of making all SPI drivers allocate space for a spi_flash structure and fill it in, udpate the API to allow callers to pass in a spi_flash structure that can be filled by the flash drivers as required. This also cleans up the interface so that the callers can maintain and free the space for spi_flash structure as required. BUG=b:38330715 Change-Id: If6f1b403731466525c4690777d9b32ce778eb563 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-06northbridge/amd/stoney: Add FT4 packageMarshall Dawson
Add package options to the CPU Kconfig that may be selected by the mainboard's Kconfig file. Stoney Ridge is available in FP4 and FT4 packages and each requires a unique binaryPI image. Default to the correct blob used by the northbridge by looking at the CPU's package. Also modify Gardenia to select the right package. See the Infrastructure Roadmap for FP4 (#53555) and FT4 (#55349) for additional details for the packages. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 7b8ed7b732b7cf5503862c5edc6537d672109aec) Change-Id: I7bb15bc4c85c5b4d3d5a6c926c4bc346a282ef27 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18989 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16binaryPI: Fix SSE regression and align stack earlyKyösti Mälkki
When allowing use of SSE instructions, stack must be aligned to 16 bytes. Adjust x86 entry to C accordingly, by pushing values to maintain the alignment. For some builds, new toolchain and GCC-6.3 could emit SSE instruction 'andps (%esp),%xmm0' with incorrectly aligned esp, raising exception and thus preventing boot. Change-Id: I452d40eadac2b743d0d8431809c9a81bf28c330a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-03-08binaryPI platforms: Drop any ACPI S3 supportKyösti Mälkki
No board with binaryPI currently supports HAVE_ACPI_RESUME. For platforms with PSP the approach is also very different from what we previously had here. Furthermore, s3_resume.[ch] files under cpu/amd/pi do not distinguish between NonVolatile and Volatile buffers of S3 storage. This means the Volatile buffer that is maintained and available in CBMEM is unnecessarily copied to SPI flash. This has been fixed on open-source AGESA directory, so development of S3 suspend support with binaryPI is better continued with that. Unfortunately there are further complications and indications that open-source AGESA may have always had a low-memory corruption issue. This has to be investigated separately before restoring or claiming S3 is supported on binaryPI. Change-Id: I81585fff7aae7bcdd55e5e95bc373e0adef43ef0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18501 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-03-07amd/pi/hudson: Move APIC enable to CPU fileMarshall Dawson
Relocate the enabling of the LAPIC out of the southbridge source and surround it with a check for CONFIG_UDELAY_LAPIC (typical for AMD systems). The LAPIC is now enabled for all cores; not only the BSP, and not only when the UART is used. This solves the problem of APs not having their APICs enabled when the timer is expected to be functional, e.g. verstage often uses do_printk_va_list() instead of do_printk() which exits early for APs when CONFIG_SQUELCH_EARLY_SMP=y. The changes were tested with two Gardenia builds, one using verstage and another with CONFIG_SQUELCH_EARLY_SMP=n. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 93ffc311165f19d4192a5489051fa4264cd8e0ad) Change-Id: Ieaecc0bf921ee0d2691a8082f2431ea4d0c33749 Signed-off-by: Marc Jones <marcj303@gmail.com> Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18436 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-12-11ACPI S3: Flip ACPI_HUGE_LOWMEM_BACKUP defaultKyösti Mälkki
Except fo nehalem, K8, f10 and f15 (non-AGESA) romstage ramstack is placed in CBMEM and ramstage loader takes care of tiny backup. Change-Id: I8477944f48ed2493d0a5e436a4088eb9fc3d59c5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17358 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07MMCONF_SUPPORT: Flip default to enabledKyösti Mälkki
Also remove separate MMCONF_SUPPORT_DEFAULT flag. Change-Id: Idf1accdb93843a8fe2ee9c09fb984968652476e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17694 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-01AMD binaryPI: Disable PCI_CFG_EXT_IOKyösti Mälkki
We don't need to do explicit pci_io_read/write operations, as we can use MMCONF everywhere. AGESA code still enables extended cf8/cfc should it be needed by payload or OS. Change-Id: Ib08028bda1b5226bb3b6b67e91f514480a9fc5ee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17536 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-01AMD binaryPI: Switch to MMCONF_SUPPORT_DEFAULTKyösti Mälkki
Vendorcode always does PCI MMCONF access once it is enabled via MSR. In coreboot proper, we don't give opportunity to make pci_read/write calls before PCI MMCONF is enabled via MSR. This happens early in romstage amd_initmmio() for all cores. Change-Id: Id6ec25706b52441259e7dc1582f9a4ce8b154083 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17534 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-25AGESA binaryPI: Fix cache-as-ram for x86_64Kyösti Mälkki
AMD_ENABLE_STACK was not called on x86_64 path for AGESA, while it was for binaryPI. Comments on BIST and cpu_init_detected were reversed, so fix those too. Change-Id: I0ddfaf51feb386a56d488c29d60171b05ff6fbc4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17551 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2016-11-22spi: Clean up SPI flash driver interfaceFurquan Shaikh
RW flag was added to spi_slave structure to get around a requirement on some AMD flash controllers that need to group together all spi volatile operations (write/erase). This rw flag is not a property or attribute of the SPI slave or controller. Thus, instead of saving it in spi_slave structure, clean up the SPI flash driver interface. This allows chipsets/mainboards (that require volatile operations to be grouped) to indicate beginning and end of such grouped operations. New user APIs are added to allow users to perform probe, read, write, erase, volatile group begin and end operations. Callbacks defined in spi_flash structure are expected to be used only by the SPI flash driver. Any chipset that requires grouping of volatile operations can select the newly added Kconfig option SPI_FLASH_HAS_VOLATILE_GROUP and define callbacks for chipset_volatile_group_{begin,end}. spi_claim_bus/spi_release_bus calls have been removed from the SPI flash chip drivers which end up calling do_spi_flash_cmd since it already has required calls for claiming and releasing SPI bus before performing a read/write operation. BUG=None BRANCH=None TEST=Compiles successfully. Change-Id: Idfc052e82ec15b6c9fa874cee7a61bd06e923fbf Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17462 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-09amd/cpu: Add details to chip namesMarshall Dawson
Newer AMD families have multiple models within them, each often requiring unique support. The chip_name files were starting to have a lot of duplication. Specify the model in the name, as well as the family. Change-Id: I236b260e2a565e212c486347c4a633eadcdf0042 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/17187 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-09AMD binaryPI: Delay ACPI S3 backup until ramstage loaderKyösti Mälkki
Change-Id: I482cf93fe5dfab95817c87c32aad33df2e0a6439 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15471 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-09ACPI S3: Remove HIGH_MEMORY_SAVE where possibleKyösti Mälkki
Add implementation to use actual requirements of ramstage size for S3 resume backup in CBMEM. The backup covers complete pages of 4 KiB. Only the required amount of low memory is backed up when ACPI_TINY_LOWMEM_BACKUP is selected for the platform. Enable this option for AGESA and binaryPI, other platforms (without RELOCATABLE_RAMSTAGE) currently keep their romstage ramstack in low memory for s3 resume path. Change-Id: Ide7ce013f3727c2928cdb00fbcc7e7e84e859ff1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15255 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-11-02cpu/amd: Update files for 00670F00Marc Jones
Add StoneyRidge specific IDs, code, whitespace, and fix Makefles and Kconfig files. Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Tested-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit 0bd1dc834792453d8e66216fa9a70afe2f7537d7) Change-Id: Id79f316a89b3baeae95e221fb872dc8a86e7b0f1 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17140 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02cpu/amd: Copy 00660F01 to 00670F00Marc Jones
Prepare for new 00670F00 (StoneyRidge) support. Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Tested-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit 87d26e05189247685df0ca6492dc3181a1bad5e8) Change-Id: Ib296ad32a061669b28dae742cac08bb75fdd0de4 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17139 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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