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coreboot
2560p
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autoport-hsw
broadwell_refcode
e6230
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haswell-mrc
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mec1322
Some coreboot project code with my work
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socket_ASB2
Age
Commit message (
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Author
2015-11-02
cpu/amd: Move model_10xxx to family_10h-family_15h
Timothy Pearson
2015-09-04
x86: remove cpu_incs as romstage Make variable
Aaron Durbin
2015-05-04
cpu: get rid of socket source code
Stefan Reinauer
2015-02-20
AMD amdfam10: Always have HT3_SUPPORT
Kyösti Mälkki
2014-12-19
AMD amdfam10: Drop EXT_CONF_SUPPORT
Kyösti Mälkki
2014-07-05
Drop redundant select CACHE_AS_RAM
Kyösti Mälkki
2013-07-10
AMD: Kconfig cleanup
Kyösti Mälkki
2013-03-22
x86: unify amd and non-amd MTRR routines
Aaron Durbin
2013-03-01
GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«
Paul Menzel
2012-10-07
Remove chip.h files without config structure
Kyösti Mälkki
2012-08-22
Auto-declare chip_operations
Kyösti Mälkki
2011-11-01
Remove XIP_ROM_BASE
Patrick Georgi
2010-12-18
SMM for AMD K8 Part 1/2
Stefan Reinauer
2010-12-08
Move "select CACHE_AS_RAM" lines from boards into CPU socket.
Uwe Hermann
2010-09-30
Rename build system variables to be more intuitive, and
Patrick Georgi
2010-09-10
Move memory type information out of some AMD sockets.
Myles Watson
2010-04-23
AMD Socket ASB2 and AM3 support.
Zheng Bao