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2016-02-18cpu/amd: Add socket FM2Damien Zammit
Change-Id: I397c908867fef7583063c8cad7b83ce53482529b Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13708 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-14cpu/amd: Update/Add license headersDamien Roth
These license headers were either not compliant with the coreboot standard or were missing completely. Change-Id: I0c46ad9ba7f3d950b3eff96ee6e9c36acbf1a3a5 Signed-off-by: Damien Roth <yves.r.roth@gmail.com> Reviewed-on: https://review.coreboot.org/13288 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05cpu/amd/fam10h-fam15h: Honor CMOS option to disable CPB (core boost)Timothy Pearson
On certain systems and CPUs Core Performance Boost (CPB) may cause sporadic system lockups. This issue is also somewhat known on the various proprietary BIOSes, therefore it seems to be a hardware incompatibility when present. Allow the user to disable CBP if needed. Change-Id: Id6395d067d48963f6c084ad0bf79e23419af24d8 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13172 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-02-05cpu/amd/fam10h-15h: Set PowerStepUp/PowerStepDown on Fam15hTimothy Pearson
Multilink Family 15h processors were being configured with an incorrect PowerStepUp/PowerStepDown value. Set the value according to the BKDG, and clean up the terrible formatting of the power_up_down() function that led to the incorrect values being overlooked until now. Also change u32 declarations to uint32_t in modified functions. Change-Id: I16e1f5205d6b5f349a3e7167dea04c9eefda4684 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13174 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-02amd/agesa/family15tn: Add Richland CPU IDLoic
Add the AMD A8-660K APU. Change-Id: I210a8ba962529c26a535965689672a46b09e325f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13510 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-02src/: Fix Kcofig symbols missing CONFIG_ prefixMartin Roth
- Add CONFIG_ prefix to two symbols. - Remove the use of the third symbol as it will never be matched. Change-Id: Ifa7f6884001cb05fb8397f193c4b08a0161f498c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13539 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-01cpu/amd/fam10h-15h: Add workaround for AMD Erratum 600Timothy Pearson
Change-Id: Ie175b5b490f77cc380536ebd737da8618d4b448b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13170 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-02-01cpu/amd/fam10h-fam15h: Add new wait_ap_stopped functionTimothy Pearson
Under certain conditions, such as when microcode updates are being performed, it is important to make sure all APs have finished updates and are halted before continuing with the boot process. Add a new wait_ap_stopped() function to allow for this functionality to be added to the appropriate mainboard romstage source files. Change-Id: Ib455c937888a58b283bd3f8fda1b486eea41b0a7 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13168 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-01cpu/amd/fam10h-15h: Fix Family 15h boot hang when BSP lift enabledTimothy Pearson
The existing code did not allow for the second core of the BSP to reside on an APIC ID other than 1, leading to a boot hang on Family 15h processors when APIC_ID_OFFSET was set to anything other than 0. Furthermore, insufficient AP stack space was allocated for AP start. Change-Id: I4ded3cfb3736149e2265848014352d7622d5042a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13158 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-29cpu/amd/fam10h-fam15h: Correctly create APIC ID on single node systemsTimothy Pearson
The existing code generated an incorrect boot APIC ID from node and core number for single node packages, leading to a boot failure when the second node was installed. Properly generate the boot APIC ID from node and core number. Change-Id: I7a00e216a6841c527b0a016fa07befb42162414a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13149 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-24cpu/amd/family_10h-family_15h: Move CBMEM storage out of CC6 save regionTimothy Pearson
The existing CBMEM TOM calculations did not account for the CC6 save region (when enabled); this resulted in CBMEM storage being placed on top of the CC6 save region, which resulted in corrupt CBMEM data and a boot hang. Change-Id: I32399da0438d7b16e05192449be625f9aa675b18 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13143 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-24cpu/amd/family_10h-family_15h: Set LDT tristate correctly on C32 socketsTimothy Pearson
The existing code unconditionally cleared the LDT tristate enable bit, which was incorrect for C32 sockets. Update the code to be in line with the BKDG recommendations. Change-Id: I8095931973ea10f1467a6621092e88c6c494565a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13142 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-23cpu/amd: remove .intel_syntaxPatrick Georgi
Replace with the more familiar AT&T syntax. Tested by sha1sum(1)ing the object files, and checking the objdump that the code in question was actually compiled. Change-Id: Ibdc024ad90c178c4846d82c5308a146dd1405165 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13133 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-20Kconfig: Remove selects that enable 'choice' symbolsMartin Roth
Selecting Kconfig symbols that were created inside a 'choice' block have no effect. Remove these so people aren't confused by them. Change-Id: I7de9131d8d8afb65f86648afb9728f09cb67e122 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12970 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07cpu/amd/microcode: Introduce CBFS access spinlock to avoid IOMMU failureTimothy Pearson
When microcode updates are enabled, this fixes an issue identical to that described in GIT hash 7b22d84d: * drivers/pc80: Add optional spinlock for nvram CBFS access Change-Id: Ib7e8cb171f44833167053ca98a85cca23021dfba Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12063 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-06cpu/amd/fam10h-15h: Add tsc_freq_mhz() functionTimothy Pearson
The AMD Family 10h/15h processors use a TSC that increments at the P0 core frequency. Allow coreboot to query the TSC frequency. Change-Id: I73ead4fd4af18991452d59985b667a54689778cd Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12834 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-12-18drivers/pc80: Add optional spinlock for nvram CBFS accessTimothy Pearson
When enabling the IOMMU on certain systems dmesg is spammed with I/O page faults like the following: AMD-Vi: Event logged [IO_PAGE_FAULT device=00:14.0 domain=0x000a address=0x000000fdf9103300 flags=0x0030] Decoding the faulting address: 0x000000fdf9103300 fdf91x Hypertransport system management region 33 SysMgtCmd (System Management Command) = 0x33 3 Base Command Type = 0x3: STPCLK (Stop Clock request) 3 SMAF (System Management Action Field) = [3:1] = 0x1 1 Signal State Bit Map = [0] = 0x1 Therefore, the error appears to be triggered by an upstream C1E request. This was eventually traced to concurrent access to the SP5100's SPI Flash controller by multiple APs during startup. Calls to the nvram read functions get_option and read_option call CBFS functions, which in turn make near-simultaneous requests to the SPI Flash controller, thus placing the SP5100 in an invalid state. This limitation is not documented in any public AMD errata, and was only discovered through considerable debugging effort. Change-Id: I4e61b1ab767b1b7958ac7c1cf20eee41d2261bef Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12061 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-15src/console: Add x86 romstage spinlock option and printk spinlock supportTimothy Pearson
This paves the way for AP printk spinlock on AMD platforms Change-Id: Ice42a0d3177736bf6e1bc601092e413601866f20 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/11958 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-01cpu/amd/fam10h-15h: Enable DFE on Family 15h HT3 linksTimothy Pearson
Decision Feedback Equalization (DFE) is a form of dynamic link training used to lower the overall error rate within the coherent fabric. Enable it on all capable HT links. Change-Id: I5e719984ddd723f9e375ff1a9d4fa1ef042cf3eb Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12072 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-12-01cpu/amd/fam10h-15h: Fix link type detection and XCS buffer count setupTimothy Pearson
The existing code did not properly detect various link attributes on Family 10h/15h processors. With the addition of new HT3- and IOMMU-specific code, proper detection has become critical to avoid system deadlocks. Fix and streamline link attribute detection. Change-Id: If63dd97f070df4aab25a1e1a34df4b1112fff4b1 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12071 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-01cpu/amd/fam10h-15h: Force iolink detect to either 1 or 0Timothy Pearson
Minor change to be more explicit about the binary state of the iolink detect variable. Change-Id: Ifd8f5f1ab28588d100e9e4b1fb0ec2525ad2f552 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12069 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-11-30cpu/amd/family_10h-family_15h: Apply missing Family 15h errata fixesTimothy Pearson
Change-Id: I132874fe5b5a8b9a87422e2f07bff03bc5863ca4 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12065 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins)
2015-11-26amd/car: don't apply Fam10h/Fam12h Errata 343 fix to Fam0FhJonathan A. Kollasch
Fixes early fault problem on Fam0Fh introduced in Change I8e01a4ab68b463efe02c27f589e0b4b719532eb5, commit 991f18475c951dcd728eb8550b10dd62938b1770. Change-Id: Id215d2822b78917939c28f7a922a94e02e5d15bf Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: https://review.coreboot.org/12528 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-11-24northbridge/amd/amdht: Add isochronous setup supportTimothy Pearson
The coherent fabric on all Family 10h/15h devices supports isochronous mode, which is required for IOMMU operation. Add initial support for isochronous operation. Change-Id: Idd7c9b94a65f856b0059e1d45f8719d9475771b6 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12042 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-24amd/amdfam10: Control Fam15h cache partitioning via nvramTimothy Pearson
Add options to control cache partitioning and overall memory performance via nvram. Change-Id: I3dd5d7f3640aee0395a68645c0242307605d3ce7 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12041 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-23cpu/amd/fam15h: Set up Link Base Channel Buffer Count registersTimothy Pearson
Change-Id: I8d616a64a5a9cf0b51288535f5050c6866d0996b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12038 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins)
2015-11-23cpu/amd: de-duplicate MSR include filesStefan Reinauer
Change-Id: I8e01a4ab68b463efe02c27f589e0b4b719532eb5 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12510 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-22cpu/amd/fam10h15h: Set up SRI to XCS Token Count registers on Family 15hTimothy Pearson
Change-Id: Ic992efad11d8e231ec85c793cf1e478bea0b9d3e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12040 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-11-22cpu/amd/family_10h-family_15h: Set up cache controls on Family 15h to ↵Timothy Pearson
improve performance Change-Id: I3df571d8091c07ac1ee29bf16b5a68585fa9eed4 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12039 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-11-22cpu/amd/family_10h-family_15h: Set up link XCS token counts on Family 15hTimothy Pearson
Change-Id: I4cf6549234041c395a18a89332d95f20a596fc3e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12033 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-11-22cpu/amd/family_10h-family_15h: Configure NB register 2Timothy Pearson
Change-Id: I55cfc96a197514212b2a4c344d3513396ebc2ad4 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12032 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-11-21cpu/amd/car/post_cache_as_ram: Avoid trailing spacesPaul Menzel
Looking at the coreboot console logs there are sometimes trailing whitespaces in the output, for example, if writing `Done` was not possible. Adapt the code, that spaces are only added when needed. Change-Id: Ia0af493ab62b6fab24e8a2629cf5fd67329e0af7 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/12357 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-21amd/family_10h-family_15h: Fix poor performance on Family 15h CPUsTimothy Pearson
Change-Id: Ieb1f1fb5653651c98764de79636669802578d5f9 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12028 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-20northbridge/amd/amdht: Add support for HT3 2.8GHz and up link frequenciesTimothy Pearson
Change-Id: Ifa1592d26ba7deb034046fd3f2a15149117d9a76 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12027 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-20cpu/amd/family_10h-family_15h: Fix incorrect revision detectionTimothy Pearson
The revision detection code for AMD Family 10h/15h was modified to use a 64-bit value instead of 32-bit in order to accomodate additional processor revisions. The FIDVID code was not updated at that point, leading to incorrect revision use during FIDVID. Change-Id: I7a881a94d62ed455415f9dfc887fd698ac919429 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12026 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-20nb/amd/amdfam10: Add HyperTransport probe filter supportTimothy Pearson
All modern Opteron processors support the HT probe filter, which helps to increase coherent fabric performance by reducing the number of HT transactions per cache probe. AMD recommends that the probe filter be enabled on all systems with more than two nodes, and it does not hurt to enable it on systems with 2 nodes. Change-Id: I00a27a828260be8685ae622cfa5a4995add95a8e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12021 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-20cpu/amd/fam10h-fam15h: Set northbridge throttle valuesTimothy Pearson
The existing code did not set the northbridge throttle values on Family 15h, leading to sporadic and random deadlocks in the crossbar per AMD notes. Properly set the northbridge throttle values on Family 15h. Change-Id: I6304b63708c65fedb9c2d46b8c862b7f0adf1102 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12025 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-11-19cpu/amd/fam10h-fam15h: Bring HT register configuration in line with BKDGTimothy Pearson
The existing HyperTransport register configuration values were incorrect in many spots. Apply the correct values from the BKDG on Family 10h and Family 15h processors. Change-Id: I009b6f478340e2dbfcda2b4534473d4397f9ecef Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12022 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-18cpu/amd/fam10h-fam15h: Update Fam15h APIC config and startup sequenceTimothy Pearson
This fixes Family 15h multiple package support; the previous code hung in CAR setup and romstage when more than one CPU package was installed for a variety of loosely related reasons. TEST: Booted ASUS KGPE-D16 with two Opteron 6328 processors and several different RDIMM configurations. Change-Id: I171197c90f72d3496a385465937b7666cbf7e308 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12020 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-16cpu/amd/fam10h-15h: Fix BSP stack corruption on 32-core Fam10 systemsTimothy Pearson
On some multi-socket AMD platforms there are too many cores for all APs to start up without stack collisions with either each other or the BSP. On such platforms a larger amount of CAR memory is also available. Allow the maximum DCACHE size to be increased via a mainboard- specific Kconfig flag. Change-Id: I72ae8f7abeb9a83b57505469922818f9ec5bdf3f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12015 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-11-15amd/model_fxx: Check FID&VID Support for the BSP (too)Urja Rannikko
Tested: Avoids crash with Sempron 2800+ on K8V-X. Change-Id: I76196176635bb0f6ac284c8cb3b72212774fdfe4 Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-on: http://review.coreboot.org/12336 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2015-11-15cpu/amd: Fix AMD Family 15h ECC initialization reliability issuesTimothy Pearson
There were numerous issues surrounding AMD ECC initialization on Family 15h processors due to the incomplete derivation from Family 10h MCT code. Bring the Family 15h ECC initialization and supporting setup code in line with the BKDG recommendations. Change-Id: I7f009b655f8500aeb22981f7020f1db74cdd6925 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12003 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-11cpu/amd: Add CC6 supportTimothy Pearson
This patch adds CC6 power save support to the AMD Family 15h support code. As CC6 is a complex power saving state that relies heavily on CPU, northbridge, and southbridge cooperation, this patch alters significant amounts of code throughout the tree simultaneously. Allowing the CPU to enter CC6 allows the second level of turbo boost to be reached, and also provides significant power savings when the system is idle due to the complete core shutdown. Change-Id: I44ce157cda97fb85f3e8f3d7262d4712b5410670 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11979 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-10cpu/amd/car: Add romstage BSP stack overrun detectionTimothy Pearson
NOTE: This commit switches CacheBase in CAR to use the DCACHE_RAM_BASE Kconfig variable. There should be no functional difference between the existing code and the new code, however hardware verfication is encouraged on lesser used architectures such as AMD Geode. Change-Id: Ia2e8f99be9df388e492a633c49df21ca1c57ba13 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11970 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-10amd/model_fxx: fix code style in FID&VID support checkUrja Rannikko
This is in AP code, fixed in preparation for copying the same check to BSP. Change-Id: I0750919d9fdb3d4e6666221ad82097e0c479cf14 Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-on: http://review.coreboot.org/12359 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-08cpu/amd/family_10h-family_15h: Increase BSP stack sizeTimothy Pearson
The additional local data storage requirements of the full DDR3 DRAM training algorithm make a BSP stack overrun a distint possibility. Increase the BSP stack size to compensate. Change-Id: I51af31442f2b77cb64a4b788751ccc7186acb283 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11972 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2015-11-08cpu/amd/family_10h-family_15h: Add Family 15h microcode fileTimothy Pearson
Change-Id: I019f94b99d2fc33e19567acecaaad93813ab6b04 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11968 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2015-11-06amd/00730F01: Add correct CPU modelKyösti Mälkki
Change-Id: I887f9eb890f1f1c6f88b7984f0520bd17be8b88b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/12284 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-06AMD binaryPI: Fix include pathsKyösti Mälkki
Do not mix open-source AGESA and binaryPI includes. Change-Id: I1e43334ba8d5a17d3580f81e023ca2c8caf86f7c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/12283 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-11-03cpu/amd/model_fxx: Backport PowerNow! core count fix from Family 10hTimothy Pearson
The K8 PowerNow! state generator does not generate _PSS objects for nodes other than the first CPU package. This patch backports the PowerNow! core count fixes for Family 10h to the K8 CPUs. Change-Id: I7b411ab75155dfb4bf51ae04301aa16fb2ae89f3 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12286 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-14 23:28:45 +0000