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2017-05-27CBMEM: Clarify CBMEM_TOP_BACKUP function usageKyösti Mälkki
The deprecated LATE_CBMEM_INIT function is renamed: set_top_of_ram -> set_late_cbmem_top Obscure term top_of_ram is replaced: backup_top_of_ram -> backup_top_of_low_cacheable get_top_of_ram -> restore_top_of_low_cacheable New function that always resolves to CBMEM top boundary, with or without SMM, is named restore_cbmem_top(). Change-Id: I61d20f94840ad61e9fd55976e5aa8c27040b8fb7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-19drivers/spi/spi_flash: Pass in flash structure to fill in probeFurquan Shaikh
Instead of making all SPI drivers allocate space for a spi_flash structure and fill it in, udpate the API to allow callers to pass in a spi_flash structure that can be filled by the flash drivers as required. This also cleans up the interface so that the callers can maintain and free the space for spi_flash structure as required. BUG=b:38330715 Change-Id: If6f1b403731466525c4690777d9b32ce778eb563 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-18AMD MTRR: Add common add_uma_resource_below_tolm()Kyösti Mälkki
Change-Id: I9eee88dc619ac5d9c77153db522a6ead65f6c9b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-28nb/amd/amdk8: Link reset_test.cArthur Heymans
This needs some extra headers in amdk8/raminit.c that were otherwise provided by that file. Change-Id: I80450e5eb32eb502b3d777c56790db90491fc995 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19360 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-04-27nb/amd/amdk8: Link raminit_f.cArthur Heymans
For this debug.c needs to be linked too. Change-Id: I9cd1ffff2c39021693fe1d5d3f90ec5f70891f57 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19030 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-04-15AGESA: Unify heap locationKyösti Mälkki
HEAP management is identical enough to move heap away from first 1MiB for all platforms. Change-Id: I4128fc084fe072fef6194d260c05592582b7b0d0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19267 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-04-06northbridge/amd/stoney: Add FT4 packageMarshall Dawson
Add package options to the CPU Kconfig that may be selected by the mainboard's Kconfig file. Stoney Ridge is available in FP4 and FT4 packages and each requires a unique binaryPI image. Default to the correct blob used by the northbridge by looking at the CPU's package. Also modify Gardenia to select the right package. See the Infrastructure Roadmap for FP4 (#53555) and FT4 (#55349) for additional details for the packages. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 7b8ed7b732b7cf5503862c5edc6537d672109aec) Change-Id: I7bb15bc4c85c5b4d3d5a6c926c4bc346a282ef27 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18989 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-05AGESA: Disable CAR with empty stackKyösti Mälkki
Calling disable_cache_as_ram() with valuables in stack is not a stable solution, as per documentation AMD_DISABLE_STACK should destroy stack in cache. Change-Id: I986bb7a88f53f7f7a0b05d4edcd5020f5dbeb4b7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18626 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-05AGESA: BIST is already preservedKyösti Mälkki
Officialy we enter with BIST in %eax, but %ebp is old backup register. Note that post_code() destroys %al. Change-Id: I77b9a80aac11ae301fdda71c2a20803d7a5fb888 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18625 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-05AGESA: Move romstage main entry under cpuKyösti Mälkki
As we now apply asmlinkage attributes to romstage_main() entry, also x86_64 passes parameters on the stack. Change-Id: If9938dbbe9a164c9c1029431499b51ffccb459c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18624 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-05AGESA: Move amd_initmmio() callKyösti Mälkki
Function enables PCI MMCONF and XIP cache, it needs to be called before giving platform any chance of calling any PCI access functions. Change-Id: Ic044d4df7b93667fa987c29c810d0bd826af87ad Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18623 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-04AGESA: Reduce typecasting in heapmanager callsKyösti Mälkki
Change-Id: Ifc065dca00ab3dfc65a314aaaf04dd2a7afcad0e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19040 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-04AGESA: Handle HEAP_CALLOUT_RUNTIME allocation more cleanlyKyösti Mälkki
This was guarded because AGESA.h only defined it starting from fam15 header files. We can simply test if it has been defined. The way coreboot currently handles this request, is to make the allocation outside the heap, since heap may not be in CBMEM and thus not available runtime. The acquired buffer from Allocate() would not be found with Locate() or Deallocate(), so move the alloc_cbmem() call for better code symmetry. Change-Id: Ibf0066913a0b73e768488c3afbeb70139a3961eb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19039 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-04AGESA: Adjust heap location for S3 resume pathKyösti Mälkki
Once we do CAR teardown between AmdInitResume() and AmdS3LateRestore() we attempt to find our heap from the temporary memory buffer instead of cache. S3 resume is essentially broken anyways and this is not yet a proper fix at all, but barely keeps system from halting on S3 resume. Offset that seems arbitrary was taken from hudson/agesawrapper.c. Change-Id: Idddf2ecde5a9d32d532071d6ba05032be730460c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19038 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-04AGESA: Refactor S3 support functionsKyösti Mälkki
Producer and consumer of these buffers now appear in same file. Also add test for uninitialized NonVolatileStorage in SPI. Change-Id: Ibbf6581a0bf1d4bffda870fc055721627b538b92 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19037 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-28AGESA: Fork for new cache-as-ram init codeKyösti Mälkki
To gradually consolidate and improve AGESA board romstages, fork the original CAR setup code as a separate file. It becomes too messy with preprocessor to attempt make changes within the same file, and at end of patchset original becomes obsolete. Change-Id: I256b675b1ab9e13c2bcc956e0d67c6c03e91f2ed Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18620 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-28AGESA: Introduce AGESA_LEGACY and its counterpartKyösti Mälkki
We define AGESA_LEGACY as an implementation of mainboard that has its romstage main completely under mainboard/ directory. We have learnt from other platforms this approach has several downsides when it comes to making platform-wide improvements. We start by creating per-family romstage.c file, which boards will gradually take into use by removing the AGESA_LEGACY Kconfig option we here apply to all of them. Change-Id: Id01931e185a023039a60af16a678de9966db8d65 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18619 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16binaryPI: Fix SSE regression and align stack earlyKyösti Mälkki
When allowing use of SSE instructions, stack must be aligned to 16 bytes. Adjust x86 entry to C accordingly, by pushing values to maintain the alignment. For some builds, new toolchain and GCC-6.3 could emit SSE instruction 'andps (%esp),%xmm0' with incorrectly aligned esp, raising exception and thus preventing boot. Change-Id: I452d40eadac2b743d0d8431809c9a81bf28c330a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-03-15AGESA f14: Fix infinite loopKyösti Mälkki
Fix regression after commit: 22f32c7 cpu/amd/agesa: Unify init files Change-Id: I36fb7369084c68577df69abc251c84dad64f7015 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18822 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2017-03-10cpu/amd/agesa: Unify init filesPaul Menzel
The init files for the AMD families using the AGESA platform initialization code are quite similar. So reduce the differences, by using the same comments, variable names, console messages, and blank lines. Change-Id: Id4a3a5c3812a34627d726cdcbe8f4781a14be724 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/18507 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-09AGESA: Log heap initialisationKyösti Mälkki
This is useful for debugging S3 issues and in general to understand AGESA memory allocator behaviour. Change-Id: I422f2620ed0023f3920b8d2949ee1c33a6c227e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18535 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2017-03-09AGESA: Fix SSE regression and align stack earlyKyösti Mälkki
When allowing use of SSE instructions, stack must be aligned to 16 bytes. Adjust x86 entry to C accordingly, by pushing values to maintain the alignment. Fixes regression with new toolchain using GCC-6.3 and ec0a393 console: Enable printk for ENV_LIBAGESA For some builds, the above-mentioned commit emitted SSE instruction 'andps (%esp),%xmm0' with incorrectly aligned esp, raising exception and thus preventing boot. Change-Id: Ief57a2ea053c7497d50903838310b7f7800bff26 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18622 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-08binaryPI platforms: Drop any ACPI S3 supportKyösti Mälkki
No board with binaryPI currently supports HAVE_ACPI_RESUME. For platforms with PSP the approach is also very different from what we previously had here. Furthermore, s3_resume.[ch] files under cpu/amd/pi do not distinguish between NonVolatile and Volatile buffers of S3 storage. This means the Volatile buffer that is maintained and available in CBMEM is unnecessarily copied to SPI flash. This has been fixed on open-source AGESA directory, so development of S3 suspend support with binaryPI is better continued with that. Unfortunately there are further complications and indications that open-source AGESA may have always had a low-memory corruption issue. This has to be investigated separately before restoring or claiming S3 is supported on binaryPI. Change-Id: I81585fff7aae7bcdd55e5e95bc373e0adef43ef0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18501 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-03-08AGESA: Move heap allocator declarationsKyösti Mälkki
Definitions are not part of ACPI S3 feature, nor do they require any AGESA headers so move them to a better location. Change-Id: I9269e9d65463463d9b8280936cf90ef76711ed4f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18616 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-03-08AMD geode: Avoid conflicting main() declarationKyösti Mälkki
Declaration of main in cpu/amd/car.h conflicts with the definition of main required for x86/postcar.c in main_decl.h. Change-Id: I19507b89a1e2ecf88ca574c560d4a9e9a3756f37 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18615 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-07amd/pi/hudson: Move APIC enable to CPU fileMarshall Dawson
Relocate the enabling of the LAPIC out of the southbridge source and surround it with a check for CONFIG_UDELAY_LAPIC (typical for AMD systems). The LAPIC is now enabled for all cores; not only the BSP, and not only when the UART is used. This solves the problem of APs not having their APICs enabled when the timer is expected to be functional, e.g. verstage often uses do_printk_va_list() instead of do_printk() which exits early for APs when CONFIG_SQUELCH_EARLY_SMP=y. The changes were tested with two Gardenia builds, one using verstage and another with CONFIG_SQUELCH_EARLY_SMP=n. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 93ffc311165f19d4192a5489051fa4264cd8e0ad) Change-Id: Ieaecc0bf921ee0d2691a8082f2431ea4d0c33749 Signed-off-by: Marc Jones <marcj303@gmail.com> Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18436 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-07AGESA: Add agesa_helper.h headerKyösti Mälkki
These definitions do not require AGESA.h include, and we will eventually remove agesawrapper.h files. Change-Id: I1b5b78409828aaf2616e177bb54a054960c3869f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18588 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-02-22src/cpu/amd: Update/Add license headers to all filesMartin Roth
Change-Id: I1e0b2b9086db6b3c2f716d9400a83eb60b2ce222 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18403 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-01-04amdfam10: Perform major include ".c" cleanupDamien Zammit
Previously, all romstages for this northbridge family would compile via 1 single C file with everything included into the romstage.c file (!) This patch separates the build into separate .o modules and links them accordingly. Currently compiles and links all fam10 roms without breaking other roms. Both DDR2 and DDR3 have been completed TESTED on REACTS: passes all boot tests for 2 boards ASUS KGPE-D16 ASUS KFSN4-DRE Some extra changes were required to make it compile otherwise there were unused functions in included "c" files. This is because I needed to exchange CIMX for the native southbridge routines. See in particular: advansus/a785e-i asus/m5a88-v avalue/eax-785e A followup patch may be required to fix the above boards. See FIXME, XXX tags Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/17625 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
2016-12-11ACPI S3: Flip ACPI_HUGE_LOWMEM_BACKUP defaultKyösti Mälkki
Except fo nehalem, K8, f10 and f15 (non-AGESA) romstage ramstack is placed in CBMEM and ramstage loader takes care of tiny backup. Change-Id: I8477944f48ed2493d0a5e436a4088eb9fc3d59c5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17358 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-11x86 SMM: Fix use with RELOCATABLE_RAMSTAGEKyösti Mälkki
The value for _size was not evaluated correctly if ramstage is relocated, make the calculation runtime. While touching it, move symbol declarations to header file. Change-Id: I4402315945771acf1c86a81cac6d43f1fe99a2a2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17784 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07MMCONF_SUPPORT: Flip default to enabledKyösti Mälkki
Also remove separate MMCONF_SUPPORT_DEFAULT flag. Change-Id: Idf1accdb93843a8fe2ee9c09fb984968652476e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17694 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-01romstage_handoff: remove code duplicationAaron Durbin
The same pattern was being used throughout the code base for initializing the romstage handoff structure. Provide a helper function to initialize the structure with the S3 resume state then utilize it at all the existing call sites. Change-Id: I1e9d588ab6b9ace67757387dbb5963ae31ceb252 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17646 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-01AMD binaryPI: Disable PCI_CFG_EXT_IOKyösti Mälkki
We don't need to do explicit pci_io_read/write operations, as we can use MMCONF everywhere. AGESA code still enables extended cf8/cfc should it be needed by payload or OS. Change-Id: Ib08028bda1b5226bb3b6b67e91f514480a9fc5ee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17536 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-01AMD binaryPI: Switch to MMCONF_SUPPORT_DEFAULTKyösti Mälkki
Vendorcode always does PCI MMCONF access once it is enabled via MSR. In coreboot proper, we don't give opportunity to make pci_read/write calls before PCI MMCONF is enabled via MSR. This happens early in romstage amd_initmmio() for all cores. Change-Id: Id6ec25706b52441259e7dc1582f9a4ce8b154083 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17534 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-01AGESA: Disable PCI_CFG_EXT_IOKyösti Mälkki
We don't need to do explicit pci_io_read/write operations, as we can use MMCONF everywhere. AGESA code still enables extended cf8/cfc should it be required by payload or OS. Change-Id: I278e5e26eb9a247f67927cbc67e04f081ca50f7b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17535 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-01AGESA: Switch to MMCONF_SUPPORT_DEFAULTKyösti Mälkki
Vendorcode always does PCI MMCONF access once it is enabled via MSR. In coreboot proper, we don't give opportunity to make pci_read/write calls before PCI MMCONF is enabled via MSR. This happens early in romstage amd_initmmio() for all cores. Change-Id: If31bc0a67b480bcc1d955632f413f5cdeec51a54 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17533 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-01AGESA f14: Consolidate early P-states settingKyösti Mälkki
Change-Id: I3feed296b6ff9908e783c1221a8f61d9c548fef4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17564 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-01AGESA f14: Consolidate XIP cacheKyösti Mälkki
Do this like fam15tn to reduce code duplication. Change-Id: I064fd27b85be7fb0c9d6918a84fc6f9b17065534 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17563 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-25AGESA binaryPI: Fix cache-as-ram for x86_64Kyösti Mälkki
AMD_ENABLE_STACK was not called on x86_64 path for AGESA, while it was for binaryPI. Comments on BIST and cpu_init_detected were reversed, so fix those too. Change-Id: I0ddfaf51feb386a56d488c29d60171b05ff6fbc4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17551 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2016-11-22spi: Clean up SPI flash driver interfaceFurquan Shaikh
RW flag was added to spi_slave structure to get around a requirement on some AMD flash controllers that need to group together all spi volatile operations (write/erase). This rw flag is not a property or attribute of the SPI slave or controller. Thus, instead of saving it in spi_slave structure, clean up the SPI flash driver interface. This allows chipsets/mainboards (that require volatile operations to be grouped) to indicate beginning and end of such grouped operations. New user APIs are added to allow users to perform probe, read, write, erase, volatile group begin and end operations. Callbacks defined in spi_flash structure are expected to be used only by the SPI flash driver. Any chipset that requires grouping of volatile operations can select the newly added Kconfig option SPI_FLASH_HAS_VOLATILE_GROUP and define callbacks for chipset_volatile_group_{begin,end}. spi_claim_bus/spi_release_bus calls have been removed from the SPI flash chip drivers which end up calling do_spi_flash_cmd since it already has required calls for claiming and releasing SPI bus before performing a read/write operation. BUG=None BRANCH=None TEST=Compiles successfully. Change-Id: Idfc052e82ec15b6c9fa874cee7a61bd06e923fbf Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17462 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-09amd/cpu: Add details to chip namesMarshall Dawson
Newer AMD families have multiple models within them, each often requiring unique support. The chip_name files were starting to have a lot of duplication. Specify the model in the name, as well as the family. Change-Id: I236b260e2a565e212c486347c4a633eadcdf0042 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/17187 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-09AMD binaryPI: Delay ACPI S3 backup until ramstage loaderKyösti Mälkki
Change-Id: I482cf93fe5dfab95817c87c32aad33df2e0a6439 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15471 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-09AGESA: Delay ACPI S3 backup until ramstage loaderKyösti Mälkki
Change-Id: I59773161f22c1ec6a52050245f9ad3e6cc74a934 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15470 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-09ACPI S3: Remove HIGH_MEMORY_SAVE where possibleKyösti Mälkki
Add implementation to use actual requirements of ramstage size for S3 resume backup in CBMEM. The backup covers complete pages of 4 KiB. Only the required amount of low memory is backed up when ACPI_TINY_LOWMEM_BACKUP is selected for the platform. Enable this option for AGESA and binaryPI, other platforms (without RELOCATABLE_RAMSTAGE) currently keep their romstage ramstack in low memory for s3 resume path. Change-Id: Ide7ce013f3727c2928cdb00fbcc7e7e84e859ff1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15255 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-11-02cpu/amd: Update files for 00670F00Marc Jones
Add StoneyRidge specific IDs, code, whitespace, and fix Makefles and Kconfig files. Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Tested-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit 0bd1dc834792453d8e66216fa9a70afe2f7537d7) Change-Id: Id79f316a89b3baeae95e221fb872dc8a86e7b0f1 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17140 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02cpu/amd: Copy 00660F01 to 00670F00Marc Jones
Prepare for new 00670F00 (StoneyRidge) support. Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Tested-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit 87d26e05189247685df0ca6492dc3181a1bad5e8) Change-Id: Ib296ad32a061669b28dae742cac08bb75fdd0de4 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17139 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-07src/cpu: Remove unnecessary whitespaceElyes HAOUAS
Change-Id: I0903b7ca9eada4beacfcdbcacddec23c3515651e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16850 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07cpu/amd/geode_gx2: Remove unnecessary semicolonElyes HAOUAS
Change-Id: I5585eac9fec5180254c7d3cc966441e9794e8390 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16858 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04src/cpu: Remove whitespace after sizeofElyes HAOUAS
Change-Id: I30b911a8444529653c8ea4a736a902143fe7ab20 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16864 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-24 22:04:31 +0000