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2019-11-27binaryPI: Drop BINARYPI_LEGACY_WRAPPER supportKyösti Mälkki
Drop all the sources that were guarded with this. Change-Id: I6c6fd19875cb57f0caf42a1a94f59efed83bfe0d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/19275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-11-27binaryPI: Drop S3_DATA_POS and S3_DATA_SIZEKyösti Mälkki
Direct SPI flash manipulation is forbidden, need to go through respective FMAP and rdev APIs. Change-Id: I765a6084fb26398008f38c0403f808bae19fdae1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37192 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-23Kconfig: comply to Linux 5.3's Kconfig language rulesPatrick Georgi
Kconfig became stricter on what it accepts, so accomodate before updating to a new release. Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-11-22cpu/amd/microcode: Remove microcode update routineKyösti Mälkki
This was only used with native amdfam10h-15h. Change-Id: Id8e06b25c6ec716c07aee46fce10903c62b6d684 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-21cpu/amd/fam10: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I3c69f158a5667783292161815f9ae61195b5e03b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36963 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20nb/amd/fam10: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: If36ef0749dbb661f731fb04829bd7e2202ebb422 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-20sb/amd/sb800: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: I1c25837f1ba05ecd58309b63a471001f4aee2fff Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36968 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20sb/amd/sb700: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: Iffa4f54b2d1b43b6710447e69061c6ed433bff1d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36967 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20cpu/nb/sb: Remove fam12Joe Moore
With removal of Torpedo mainboard, this code is no longer necessary. This also removes fam12 support from northbridge and SB900 from southbridge. Change-Id: I8a30461278844d0d9ad4320f0e952774c4fd644f Signed-off-by: Joe Moore <awokd@danwin1210.me> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-11-11AGESA: Select CBMEM_STAGE_CACHE with HAVE_ACPI_RESUMEKyösti Mälkki
Fix regression with commit 0a4457f lib/stage_cache: Refactor Kconfig options AGESA platforms fail to resume from S3 suspend with CBMEM_STAGE_CACHE=n. For the time being the root cause is unknown. Change-Id: I11db0c883b6e39473d02e92b14cb3c6302aa728e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-01lib/cbmem_top: Add a common cbmem_top implementationArthur Heymans
This adds a common cbmem_top implementation to all coreboot target. In romstage a static variable will be used to cache the result of cbmem_top_romstage. In ramstage if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is set a global variable needs to be populated by the stage entry with the value passed via the calling arguments. if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is not set the same implementation as will be used as in romstage. Change-Id: Ie767542ee25483acc9a56785ce20a885e9a63098 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-28src/cpu: Use 'include <stdlib.h>' when appropriateElyes HAOUAS
Also: add some missing includes spotted by Jenkins. Including <types.h>, is supposed to provide stdint and stddef. Change-Id: I7bd999b59d1c0bdfa5999bf5805576f94c9a2390 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27src/[arch-lib]: change "unsigned" to "unsigned int"Martin Roth
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ibb7b48a7a144421aff29acbb7ac30968ae5fe5ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/36329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-27cpu/amd/*/*/acpi/: Use 'Device()' instead of 'Processor()'Elyes HAOUAS
Processor() operator is deprecated, use Device() instead. Found-by: ACPICA 20191018 Change-Id: I4541372a98f05d3e915c74bc28f41309754014e4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36258 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-17cpu/amd/{agesa,pi}: Select NO_FIXED_XIP_ROM_SIZEArthur Heymans
AGESA and binaryPI set the whole CACHE_ROM_SIZE to WRPROT during the romstage and do not reference the CONFIG_XIP_ROM_SIZE symbol. Change-Id: I548b9c9066d825c2f03749353b9990b2efddfd9c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-09-29amdfam_10h-15h: Use ENV_PCI_SIMPLE_DEVICEKyösti Mälkki
Change-Id: I265d50af1099ae4449b5adebcf21e2043aa02c7a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35654 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-26cpu/amd/pi/00730F01: Clean up microcode update from __PRE_RAM__Kyösti Mälkki
It is only called in ramstage. Even if it was called in romstage, execution flow is such that BSP and AP CPUs should not be able to enter update_microcode() routine concurrently. Also the Kconfig guarding the spin_lock() calls are not selected nor are the lock variables declared for these platforms. Change-Id: I1c2e106f10e8420e942b3ed082c677c0db95557c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35586 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-15{cpu,device,drivers}: Remove unused include <device/pci_ops.h>Elyes HAOUAS
Change-Id: I68da75e3afa2f66aff9961728d4a76bc3e175fce Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33527 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-11arch/x86: Drop _car_relocatable_data symbolsKyösti Mälkki
These have become aliases to _car_global_[start|end]. Change-Id: Ibdcaaafdc0e4c6df4a795474903768230d41680d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-09-10AUTHORS: Move src/cpu/amd copyrights into AUTHORS fileMartin Roth
As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I77275adb7c15b242e319805b8a60b7755fa25db5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-26amdfam10: Remove use of __PRE_RAM__Kyösti Mälkki
Change-Id: I4215b27332034a3c07052db92e4abae55c3fe967 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-21AMD fam10: Remove HAVE_ACPI_RESUME supportKyösti Mälkki
Change-Id: I62bbba8cfe515b3cae413582ff8d062a20e6741b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/15474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-18amdfam10-15: Rename DCACHE_BSP_STACK_SIZEKyösti Mälkki
The original name DCACHE_BSP_STACK_SIZE will be exclusively used to define the fixed size of BSP stack when it is located near the beginning of CAR region. This implementation has the stack located at the very end of CAR region. Remove other fam10-15 exclusive configs from global space. Change-Id: I8b92891be2ed62944a9eddde39ed20a12f4875c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-13cpu/x86: Move some SMM function declarationsKyösti Mälkki
Change-Id: I9a4e57f8fd032f2824eab0e5b59d635710e3e24b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-08-11arch/x86: Flip option NO_CAR_GLOBAL_MIGRATIONKyösti Mälkki
It is easier to track CAR_GLOBAL_MIGRATION which is the approach to be deprecated with the next release. This change enforces new policy; POSTCAR_STAGE=y is not allowed together with CAR_GLOBAL_MIGRATION=y. Change-Id: I0dbad6a14e68bf566ac0f151dc8ea259e5ae2250 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-08-10src: Include <stdint.h> instead of <inttypes.h>Jacob Garber
The <inttypes.h> header currently does nothing but include the definitions from <stdint.h>, so let's #include that directly instead. Change-Id: I9d83ad37d0d7300a093001596ce3f0b3830c5701 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-12src: Add missing include <device/pci_ops.h>Elyes HAOUAS
Change-Id: Iae73fc1557fb310dacbbf8bc486dc3cc5249d9e7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33526 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-10cpu/amd: Remove empty smm_lock()Kyösti Mälkki
Change-Id: I599d1d7e28f3a6439b04ef9bd38f671e1a876e92 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-07-09arch/x86: Flip HAVE_MONOTONIC_TIMER defaultKyösti Mälkki
Change-Id: Id56139a3d0840684b13179821a77bc8ae28e05ae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-09cpu/x86: Declare SMM_ASEGKyösti Mälkki
This is really an inverse of SMM_TSEG to flag platforms that should potentially move away from ASEG implementation. Change-Id: I3b9007c55c75a59a9e6acc0a0e701300f7d21f87 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-09arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-classKyösti Mälkki
Build of the entire smm-class is skipped if we have HAVE_SMI_HANDLER=n. Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34125 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-07lib/romstage_stack.c: Remove fileKyösti Mälkki
After platforms have moved to POSTCAR_STAGE=y the only remaining user is binaryPI now. Make it simpler. Change-Id: Ia70c5c85e06c42f965fb7204b633db9b619e2e84 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-06-28cpu/amd/family_10h-family_15h: Remove dead assignmentJacob Garber
Pstate_num is initialized later when it is used as a loop index, so this duplicate assignment can be removed. Change-Id: I71429bd3306139a823ed39e751d779e4d874f657 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: scan-build 8.0.0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-22src/cpu: Use 'include <stdlib.h>' when appropriateElyes HAOUAS
Change-Id: I44346594bc106eed73a1268b82f026b69e5f4512 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-21cpu: Add missing #include <commonlib/helpers.h>Elyes HAOUAS
ALIGN and ALIGN_UP needs 'helpers.h' Change-Id: Ib3a9e0d6caff69f4b0adb54364b47cc6ac52a610 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-21cpu/amd: use ALIGN_UP instead of ALIGN for better readabilityFelix Held
Change-Id: Icef97ea764567a311b4cd63b65ad584ed0360152 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-06-21src/cpu/amd/pi/00730F01: Add microcode update infrastructure for fam16h PIMichał Żygowski
Code is based on microcode update procedure from fam10-15h with necessary microcode blob structure updates for fam16h. Currently updating microcode in romstage seem to be impossible. AGESA is overriding the microcode patch regardles of the current microcode revision patched on CPU. Use ramstage CPU init procedures to update microcode easily. Tested with microcode blob 07030106 released 2018-02-09 from platomav/CPUMicrocodes GitHub repository on apu2 platform. TEST=boot Linux kernel 4.14.50 on PC Engines apu2 and run dmesg to see patch_level=0x07030106 on all cores Change-Id: Ic15cba06f3cd9cfbc538b6764b158fa699f0ecf6 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29272 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21cpu/amd/family_10h-family_15h: Fix 'if' condition identical branchesElyes HAOUAS
Change-Id: I1c937a62388c38090ee2cc3228973cfb8361bac7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-06-03cpu/amd/family_10h-family_15h: Remove variable set but not usedElyes HAOUAS
Change-Id: Ifc63ec5b588f8edcec5eda343ec9694332845045 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33006 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29src/{include,arch,cpu,lib}: Add missing 'include <types.h>'Elyes HAOUAS
<types.h> is supposed to provide <stdint.h> and <stddef.h>. So when <types.h> is included, <stdint.h> and/or <stddef.h> is removed. Change-Id: I57aead27806e307b9827fc7ee2cd663f12ee6e5e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-23cpu/amd/quadcore: Remove variable set but not usedElyes HAOUAS
Change-Id: I73f35ea80976ab445c797c4800b1e2fd24d34fdf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32893 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23src: Add missing include 'console.h'Elyes HAOUAS
Change-Id: Ie21c390ab04adb5b05d5f9760d227d2a175ccb56 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-29src: Use include <reset.h> when appropriateElyes HAOUAS
Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-25Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX)Julius Werner
This patch cleans up remaining uses of raw boolean Kconfig values I could find by wrapping them with CONFIG(). The remaining naked config value warnings in the code should all be false positives now (although the process was semi-manual and involved some eyeballing so I may have missed a few). Change-Id: Ifa0573a535addc3354a74e944c0920befb0666be Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-20src: Use 'include <string.h>' when appropriateElyes HAOUAS
Drop 'include <string.h>' when it is not used and add it when it is missing. Also extra lines removed, or added just before local includes. Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-06src: Drop unused include <arch/acpi.h>Elyes HAOUAS
Change-Id: I1f44ffeb54955ed660162a791c6281f292b1116a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-04device/mmio.h: Add include file for MMIO opsKyösti Mälkki
MMIO operations are arch-agnostic so the include path should not be arch/. Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
Change-Id: I91158452680586ac676ea11c8589062880a31f91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31692 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04arch/x86/acpi: Remove obsolete acpi_gen_regaddr resv fieldElyes HAOUAS
Since ACPI v2.c, this field is access_size. Currently, coreboot is using ACPI v3,so we can drop '.resv' field. Change-Id: I7b3b930861669bb05cdc8e81f6502476a0568fe0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 09:39:22 +0000