summaryrefslogtreecommitdiff
path: root/src/cpu/intel/haswell
AgeCommit message (Expand)Author
2015-05-21Remove address from GPLv2 headersPatrick Georgi
2015-05-19intel/haswell: Drop MONOTONIC_TIMER_MSRPatrick Georgi
2015-05-053rdparty: move to 3rdparty/blobsPatrick Georgi
2015-05-053rdparty: Move to blobsPatrick Georgi
2015-05-05haswell: Link stage_cache_external_region into ramstage, tooSol Boucher
2015-04-30cpu/intel/haswell: remove dependency on socket_rpga989Matt DeVillier
2015-04-22coreboot: common stage cacheAaron Durbin
2015-03-17haswell: Fix monotonic timer integrationStefan Reinauer
2015-02-28cpu/intel: (non-FSP) Remove microcode updates from treeAlexandru Gagniuc
2015-02-28cpu/intel (non-FSP): Use microcode from blobs repositoryAlexandru Gagniuc
2015-02-16acpi: Generate valid ACPI processor objectsTimothy Pearson
2015-02-11cpu/intel: >= nehalem: add comments to msr finalize'sAlexander Couzens
2015-01-27CBMEM: Always use DYNAMIC_CBMEMKyösti Mälkki
2015-01-27CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEMKyösti Mälkki
2015-01-27vboot2: add verstageStefan Reinauer
2014-12-02Replace hlt with halt()Patrick Georgi
2014-11-30Replace hlt() loops with halt()Patrick Georgi
2014-11-15chromeos: provide stub functions for !CONFIG_VBOOT_VERIFY_FIRMWAREAaron Durbin
2014-11-09haswell: Move to implicit length patchingVladimir Serbinenko
2014-10-27{arch,cpu,drivers,ec}: Don't hide pointers behind typedefsEdward O'Callaghan
2014-10-19x86 romstage: Move stack just below RAMTOPKyösti Mälkki
2014-10-19haswell baytrail: Enable RELOCATABLE_RAMSTAGEKyösti Mälkki
2014-10-16ACPI: Remove CONFIG_GENERATE_ACPI_TABLESVladimir Serbinenko
2014-08-12cpu/intel/XXX/acpi.c: Fix coding style violationMartin Roth
2014-08-04cpu/intel: Fix out-of-bounds read due to off-by-one in conditionEdward O'Callaghan
2014-07-10intel/haswell: add vmx support w/Kconfig optionMatt DeVillier
2014-07-08cpu: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
2014-07-05intel: Make monotonic timer a first class citizenEdward O'Callaghan
2014-05-10Replace SERIAL_CPU_INIT with PARALLEL_CPU_INITKyösti Mälkki
2014-05-06Introduce stage-specific architecture for corebootFurquan Shaikh
2014-05-05haswell: move to mp_init libraryAaron Durbin
2014-05-03Move ARCH_* from board/Kconfig to cpu or soc Kconfig.Furquan Shaikh
2014-03-20rmodules: use rmodtool to create rmodulesAaron Durbin
2014-02-25Remove CACHE_ROM.Vladimir Serbinenko
2014-02-16haswell: backup the default SMM region on resumeAaron Durbin
2014-02-15coreboot: infrastructure for different ramstage loadersAaron Durbin
2014-02-12PCI: Drop includes under cpuKyösti Mälkki
2014-01-30coreboot: config to cache ramstage outside CBMEMAaron Durbin
2014-01-30vboot: provide empty vboot_verify_firmware()Aaron Durbin
2014-01-26src/cpu: Fix spelling of MTTR to MTRRPaul Menzel
2014-01-23intel/microcode: Remove leftover MICROCODE_INCLUDE_PATH.Vladimir Serbinenko
2014-01-16cpu/intel: Remove dummy terminators from microcode blobsAlexandru Gagniuc
2014-01-15nehalem/sandy/ivy/haswell: Enable WRPROT cache for all of flashKyösti Mälkki
2014-01-15Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRRKyösti Mälkki
2013-12-21haswell: Update microcode revisionDuncan Laurie
2013-12-13cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFSAlexandru Gagniuc
2013-12-12haswell: Export functions for CPU family+model and steppingDuncan Laurie
2013-12-12haswell: Update ULT microcode to rev 14hDuncan Laurie
2013-12-07haswell: VR controller configurationAaron Durbin
2013-12-07haswell: Misc power management setup and fixesDuncan Laurie
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-27 02:50:32 +0000