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path: root/src/cpu/intel/model_2065x/cache_as_ram.inc
AgeCommit message (Expand)Author
2018-04-09intel/nehalem post-car: Use postcar_frame for MTRR setupKyösti Mälkki
2017-06-07Use more secure HTTPS URLs for coreboot sitesPaul Menzel
2016-11-11intel cache-as-ram: Unify stack setupKyösti Mälkki
2016-07-22intel car: Unify postcodesKyösti Mälkki
2016-07-22intel car: Unify whitespace and comment fixesKyösti Mälkki
2016-06-22Ignore RAMTOP for MTRRsKyösti Mälkki
2016-06-22intel/model_2065x: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
2016-06-17Fix some cbmem.h includesKyösti Mälkki
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-10-15cpu/mtrr.h: Fix macro names for MTRR registersAlexandru Gagniuc
2015-07-07x86: Drop -Wa,--divideStefan Reinauer
2015-06-08Remove empty lines at end of fileElyes HAOUAS
2015-05-21Remove address from GPLv2 headersPatrick Georgi
2014-10-19x86 romstage: Move stack just below RAMTOPKyösti Mälkki
2014-07-19intel/model_2065x: Remove dead code.Vladimir Serbinenko
2014-04-26Rename coreboot_ram stage to ramstageFurquan Shaikh
2014-01-15Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRRKyösti Mälkki
2013-11-23Remove MRC variables from 2065x CAR init.Vladimir Serbinenko
2013-07-10usbdebug: Put ehci_debug_info in CAR_GLOBALKyösti Mälkki
2013-06-13Add support for Intel Nehalem CPUVladimir Serbinenko
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