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Some coreboot project code with my work
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intel
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model_2065x
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cache_as_ram.inc
Age
Commit message (
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Author
2017-06-07
Use more secure HTTPS URLs for coreboot sites
Paul Menzel
2016-11-11
intel cache-as-ram: Unify stack setup
Kyösti Mälkki
2016-07-22
intel car: Unify postcodes
Kyösti Mälkki
2016-07-22
intel car: Unify whitespace and comment fixes
Kyösti Mälkki
2016-06-22
Ignore RAMTOP for MTRRs
Kyösti Mälkki
2016-06-22
intel/model_2065x: Prepare for dynamic CONFIG_RAMTOP
Kyösti Mälkki
2016-06-17
Fix some cbmem.h includes
Kyösti Mälkki
2015-10-31
tree: drop last paragraph of GPL copyright header
Patrick Georgi
2015-10-15
cpu/mtrr.h: Fix macro names for MTRR registers
Alexandru Gagniuc
2015-07-07
x86: Drop -Wa,--divide
Stefan Reinauer
2015-06-08
Remove empty lines at end of file
Elyes HAOUAS
2015-05-21
Remove address from GPLv2 headers
Patrick Georgi
2014-10-19
x86 romstage: Move stack just below RAMTOP
Kyösti Mälkki
2014-07-19
intel/model_2065x: Remove dead code.
Vladimir Serbinenko
2014-04-26
Rename coreboot_ram stage to ramstage
Furquan Shaikh
2014-01-15
Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR
Kyösti Mälkki
2013-11-23
Remove MRC variables from 2065x CAR init.
Vladimir Serbinenko
2013-07-10
usbdebug: Put ehci_debug_info in CAR_GLOBAL
Kyösti Mälkki
2013-06-13
Add support for Intel Nehalem CPU
Vladimir Serbinenko