| Age | Commit message (Expand) | Author |
|---|---|---|
| 2014-10-19 | x86 romstage: Move stack just below RAMTOP | Kyösti Mälkki |
| 2014-04-26 | Rename coreboot_ram stage to ramstage | Furquan Shaikh |
| 2014-01-15 | Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR | Kyösti Mälkki |
| 2013-07-10 | usbdebug: Put ehci_debug_info in CAR_GLOBAL | Kyösti Mälkki |
| 2013-05-08 | copy_and_run: drop boot_complete parameter | Stefan Reinauer |
| 2013-03-01 | GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« | Paul Menzel |
| 2012-07-04 | Intel cpus: Extend cache to cover complete Flash Device | Kyösti Mälkki |
| 2012-07-04 | Intel cpus: use CPU_ADDR_BITS from Kconfig during CAR | Kyösti Mälkki |
| 2012-04-25 | Replace cache control magic numbers with symbols | Patrick Georgi |
| 2012-04-05 | Add support for Intel Sandybridge CPU | Stefan Reinauer |
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index : coreboot | |
| Some coreboot project code with my work | vimacs |
| summaryrefslogtreecommitdiff |