coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2012-07-26	Drop CONFIG_CPU_MODEL_NAME and fix CPU name displayed in logs	Stefan Reinauer
2012-07-26	Enable Microcode in CBFS for all SandyBridge/IvyBridge systems	Stefan Reinauer
2012-07-25	Fix comment to reference IvyBridge, too	Stefan Reinauer
2012-07-25	Include SandyBridge Microcode when IvyBridge is enabled	Stefan Reinauer
2012-07-24	CPU: Set flex ratio to nominal TDP ratio in bootblock	Duncan Laurie
2012-07-24	CPU: Update ivybridge PP1 current limit value	Duncan Laurie
2012-07-24	CPU: Add basic support for Nominal Configurable TDP	Duncan Laurie
2012-07-24	Config changes to support microcode in CBFS	Vadim Bendebury
2012-07-24	Add code to read Intel microcode from CBFS	Vadim Bendebury
2012-07-24	Rename microcode include file to be model agnostic	Vadim Bendebury
2012-07-24	Properly identify ACPI C3 states in _CST table.	Duncan Laurie
2012-07-24	Remove code that enables/disables VMX in coreboot on chromebooks.	Ronald G. Minnich
2012-07-04	Intel cpus: Extend cache to cover complete Flash Device	Kyösti Mälkki
2012-07-04	Intel cpus: use CPU_ADDR_BITS from Kconfig during CAR	Kyösti Mälkki
2012-07-02	remove CONFIG_SERIAL_CPU_INIT	Sven Schnelle
2012-07-02	Use broadcast SIPI to startup siblings	Sven Schnelle
2012-05-29	Drop config variable CPU_MODEL_INDEX	Stefan Reinauer
2012-04-30	Fix up Sandybridge C state generation code	Stefan Reinauer
2012-04-26	Revamp Intel microcode update code	Stefan Reinauer
2012-04-25	Replace cache control magic numbers with symbols	Patrick Georgi
2012-04-05	Add support for Intel Sandybridge CPU	Stefan Reinauer