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path: root/src/cpu/intel/model_206ax
AgeCommit message (Expand)Author
2018-10-30src: Add missing include <stdint.h>Elyes HAOUAS
2018-10-11src: Move common IA-32 MSRs to <cpu/x86/msr.h>Elyes HAOUAS
2018-10-05src: Fix MSR_PKG_CST_CONFIG_CONTROL register nameElyes HAOUAS
2018-09-26cpu/intel/model_206ax: detect number of MCE banksDan Elkouby
2018-08-09src/cpu: Fix typoElyes HAOUAS
2018-07-28nb/intel/sandybridge: Move CPU report to cpu folderPatrick Rudolph
2018-07-28intel/sandybridge: Don't hardcode platform typePatrick Rudolph
2018-06-21Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location"Arthur Heymans
2018-06-05cpu/intel/model_206ax: Switch to POSTCAR_STAGEArthur Heymans
2018-06-05cpu/intel/car/non-evict: Prepare for some POSTCAR_STAGE supportArthur Heymans
2018-04-30cpu/intel: Get rid of device_tElyes HAOUAS
2018-04-11Revert "model_206ax: Use parallel MP init"Arthur Heymans
2018-04-11model_206ax: Use parallel MP initArthur Heymans
2018-04-10cpu/intel/sandybridge: Put stage cache into TSEGArthur Heymans
2018-02-27sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common locationArthur Heymans
2017-11-23Constify struct cpu_device_id instancesJonathan Neuschäfer
2017-08-19arch/x86: Clean up CONFIG_SMP and MAX_CPUS testKyösti Mälkki
2017-06-28cpu/intel: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
2017-06-09cpu/intel/model_206ax: Use tsc monotonic timerPatrick Rudolph
2017-06-07Use more secure HTTPS URLs for coreboot sitesPaul Menzel
2017-03-16cpu/intel: Add int to unsignedLee Leahy
2017-03-16cpu/intel: Fix the spacing issuesLee Leahy
2017-03-16cpu/intel: Indent with tabsLee Leahy
2016-12-27cpu/intel/common: Add/Use common function to set virtualizationMatt DeVillier
2016-12-09intel/sandybridge: Use postcar_frame for MTRR setupKyösti Mälkki
2016-11-20intel sandy/ivy: Increase XIP cache with USE_NATIVE_RAMINITKyösti Mälkki
2016-11-18intel/sandybridge post-car: Redo MTRR settings and stack selectionKyösti Mälkki
2016-11-11intel cache-as-ram: Unify stack setupKyösti Mälkki
2016-11-11intel/sandybridge: Use common ACPI S3 recoveryKyösti Mälkki
2016-08-23src/cpu: Capitalize CPU, APIC and IOAPIC typo fixElyes HAOUAS
2016-07-31src/cpu: Capitalize CPUElyes HAOUAS
2016-07-31src/cpu: Capitalize ROM and RAMElyes HAOUAS
2016-07-26intel sandy/ivy: Redefine DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZEKyösti Mälkki
2016-07-22intel car: Unify postcodesKyösti Mälkki
2016-07-22intel car: Unify whitespace and comment fixesKyösti Mälkki
2016-06-22Ignore RAMTOP for MTRRsKyösti Mälkki
2016-06-22intel/model_206ax: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
2016-06-17intel/model_206ax: Move platform specific definesKyösti Mälkki
2016-06-17Move definitions of HIGH_MEMORY_SAVEKyösti Mälkki
2016-03-08x86 chipsets: utilize x86_setup_mtrrs_with_detect()Aaron Durbin
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-10-31sandybridge: Disable parallel CPU initializationNico Huber
2015-10-15cpu/mtrr.h: Fix macro names for MTRR registersAlexandru Gagniuc
2015-09-30cpu: microcode: Use microcode stored in binary formatAlexandru Gagniuc
2015-09-04x86: remove cpu_incs as romstage Make variableAaron Durbin
2015-08-25Intel: Remove CACHE_MRC_BIN - 'selected' everywhere in KconfigMartin Roth
2015-07-07x86: Drop -Wa,--divideStefan Reinauer
2015-06-10model_206ax: Fix APIC map when HT is disabled.Vladimir Serbinenko
2015-06-09Create i945-ivy smm tseg init based on ivy code.Vladimir Serbinenko
2015-06-08Remove empty lines at end of fileElyes HAOUAS
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