coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2019-01-24	cpu/intel/model_206ax: Remove the notion of sockets	Arthur Heymans
2019-01-22	cpu/intel/model_206ax: Use parallel MP init	Arthur Heymans
2018-12-20	cpu/intel/common: decouple IA32_FEATURE_CONTROL lock from set_vmx()	Matt DeVillier
2018-12-13	cpuid: Add helper function for cpuid(1) functions	Subrata Banik
2018-11-30	cpu/intel/common: Use a common acpi/cpu.asl file	Arthur Heymans
2018-11-30	cpu/intel/model_206{5,a}x: Rework acpi/cpu.asl	Arthur Heymans
2018-11-12	src: Remove unneeded include "{arch,cpu}/cpu.h"	Elyes HAOUAS
2018-10-30	src: Add missing include <stdint.h>	Elyes HAOUAS
2018-10-11	src: Move common IA-32 MSRs to <cpu/x86/msr.h>	Elyes HAOUAS
2018-10-05	src: Fix MSR_PKG_CST_CONFIG_CONTROL register name	Elyes HAOUAS
2018-09-26	cpu/intel/model_206ax: detect number of MCE banks	Dan Elkouby
2018-08-09	src/cpu: Fix typo	Elyes HAOUAS
2018-07-28	nb/intel/sandybridge: Move CPU report to cpu folder	Patrick Rudolph
2018-07-28	intel/sandybridge: Don't hardcode platform type	Patrick Rudolph
2018-06-21	Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location"	Arthur Heymans
2018-06-05	cpu/intel/model_206ax: Switch to POSTCAR_STAGE	Arthur Heymans
2018-06-05	cpu/intel/car/non-evict: Prepare for some POSTCAR_STAGE support	Arthur Heymans
2018-04-30	cpu/intel: Get rid of device_t	Elyes HAOUAS
2018-04-11	Revert "model_206ax: Use parallel MP init"	Arthur Heymans
2018-04-11	model_206ax: Use parallel MP init	Arthur Heymans
2018-04-10	cpu/intel/sandybridge: Put stage cache into TSEG	Arthur Heymans
2018-02-27	sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location	Arthur Heymans
2017-11-23	Constify struct cpu_device_id instances	Jonathan Neuschäfer
2017-08-19	arch/x86: Clean up CONFIG_SMP and MAX_CPUS test	Kyösti Mälkki
2017-06-28	cpu/intel: add IS_ENABLED() around Kconfig symbol references	Martin Roth
2017-06-09	cpu/intel/model_206ax: Use tsc monotonic timer	Patrick Rudolph
2017-06-07	Use more secure HTTPS URLs for coreboot sites	Paul Menzel
2017-03-16	cpu/intel: Add int to unsigned	Lee Leahy
2017-03-16	cpu/intel: Fix the spacing issues	Lee Leahy
2017-03-16	cpu/intel: Indent with tabs	Lee Leahy
2016-12-27	cpu/intel/common: Add/Use common function to set virtualization	Matt DeVillier
2016-12-09	intel/sandybridge: Use postcar_frame for MTRR setup	Kyösti Mälkki
2016-11-20	intel sandy/ivy: Increase XIP cache with USE_NATIVE_RAMINIT	Kyösti Mälkki
2016-11-18	intel/sandybridge post-car: Redo MTRR settings and stack selection	Kyösti Mälkki
2016-11-11	intel cache-as-ram: Unify stack setup	Kyösti Mälkki
2016-11-11	intel/sandybridge: Use common ACPI S3 recovery	Kyösti Mälkki
2016-08-23	src/cpu: Capitalize CPU, APIC and IOAPIC typo fix	Elyes HAOUAS
2016-07-31	src/cpu: Capitalize CPU	Elyes HAOUAS
2016-07-31	src/cpu: Capitalize ROM and RAM	Elyes HAOUAS
2016-07-26	intel sandy/ivy: Redefine DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE	Kyösti Mälkki
2016-07-22	intel car: Unify postcodes	Kyösti Mälkki
2016-07-22	intel car: Unify whitespace and comment fixes	Kyösti Mälkki
2016-06-22	Ignore RAMTOP for MTRRs	Kyösti Mälkki
2016-06-22	intel/model_206ax: Prepare for dynamic CONFIG_RAMTOP	Kyösti Mälkki
2016-06-17	intel/model_206ax: Move platform specific defines	Kyösti Mälkki
2016-06-17	Move definitions of HIGH_MEMORY_SAVE	Kyösti Mälkki
2016-03-08	x86 chipsets: utilize x86_setup_mtrrs_with_detect()	Aaron Durbin
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-10-31	sandybridge: Disable parallel CPU initialization	Nico Huber
2015-10-15	cpu/mtrr.h: Fix macro names for MTRR registers	Alexandru Gagniuc