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coreboot
2560p
820g2
autoport-hsw
broadwell_refcode
e6230
e7240_bdw
haswell-mrc
hp820g1
hp9480m
mec1322
Some coreboot project code with my work
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model_6ex
Age
Commit message (
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Author
2016-08-23
src/cpu: Capitalize CPU, APIC and IOAPIC typo fix
Elyes HAOUAS
2016-07-31
src/cpu: Capitalize CPU
Elyes HAOUAS
2016-07-26
intel car: Use MTRR WRPROT type for XIP cache
Kyösti Mälkki
2016-07-22
intel car: Unify postcodes
Kyösti Mälkki
2016-07-22
intel car: Unify whitespace and comment fixes
Kyösti Mälkki
2016-07-22
intel car: Remove guard on XIP_ROM_SIZE
Kyösti Mälkki
2016-06-22
Ignore RAMTOP for MTRRs
Kyösti Mälkki
2016-06-22
intel cache-as-ram: Fix comment about MTRRs
Kyösti Mälkki
2016-06-21
intel/model_6ex: Prepare for dynamic CONFIG_RAMTOP
Kyösti Mälkki
2015-10-31
tree: drop last paragraph of GPL copyright header
Patrick Georgi
2015-10-15
cpu/mtrr.h: Fix macro names for MTRR registers
Alexandru Gagniuc
2015-09-30
cpu: microcode: Use microcode stored in binary format
Alexandru Gagniuc
2015-07-07
x86: Drop -Wa,--divide
Stefan Reinauer
2015-06-08
Remove empty lines at end of file
Elyes HAOUAS
2015-05-21
Remove address from GPLv2 headers
Patrick Georgi
2015-05-05
3rdparty: move to 3rdparty/blobs
Patrick Georgi
2015-05-05
3rdparty: Move to blobs
Patrick Georgi
2015-02-28
cpu/intel: (non-FSP) Remove microcode updates from tree
Alexandru Gagniuc
2015-02-28
cpu/intel (non-FSP): Use microcode from blobs repository
Alexandru Gagniuc
2015-01-27
vboot2: add verstage
Stefan Reinauer
2014-10-27
{arch,cpu,drivers,ec}: Don't hide pointers behind typedefs
Edward O'Callaghan
2014-10-19
x86 romstage: Move stack just below RAMTOP
Kyösti Mälkki
2014-07-08
cpu: Trivial - drop trailing blank lines at EOF
Edward O'Callaghan
2014-05-06
Introduce stage-specific architecture for coreboot
Furquan Shaikh
2014-05-03
Move ARCH_* from board/Kconfig to cpu or soc Kconfig.
Furquan Shaikh
2014-02-12
PCI: Drop includes under cpu
Kyösti Mälkki
2014-01-16
cpu/intel: Remove dummy terminators from microcode blobs
Alexandru Gagniuc
2014-01-16
cpu/intel: Make all Intel CPUs load microcode from CBFS
Alexandru Gagniuc
2014-01-15
Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR
Kyösti Mälkki
2013-07-11
usbdebug: Drop old includes
Kyösti Mälkki
2013-07-10
usbdebug: Put ehci_debug_info in CAR_GLOBAL
Kyösti Mälkki
2013-06-14
usbdebug: Drop temporary disables of log output
Kyösti Mälkki
2013-05-08
copy_and_run: drop boot_complete parameter
Stefan Reinauer
2013-03-01
GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«
Paul Menzel
2013-02-09
speedstep: Deduplicate some MSR identifiers
Patrick Georgi
2012-11-27
Get rid of drivers class
Patrick Georgi
2012-11-01
Merge cpu/intel/acpi.h into cpu/intel/speedstep.h
Nico Huber
2012-08-09
Synchronize rdtsc instructions
Stefan Reinauer
2012-07-31
Revert "Use broadcast SIPI to startup siblings"
Sven Schnelle
2012-07-04
Intel cpus: Extend cache to cover complete Flash Device
Kyösti Mälkki
2012-07-04
Intel cpus: delete dead CAR code and whitespace fixes
Kyösti Mälkki
2012-07-04
Intel cpus: use CPU_ADDR_BITS from Kconfig during CAR
Kyösti Mälkki
2012-07-02
Use broadcast SIPI to startup siblings
Sven Schnelle
2012-04-25
Replace cache control magic numbers with symbols
Patrick Georgi
2012-03-17
Intel cpus: Include CAR from socket
Kyösti Mälkki
2012-02-16
Intel cpus: use CPU_PHYSMASK_HI define in CAR
Kyösti Mälkki
2012-02-10
Intel cpus: apply un-written naming rules
Kyösti Mälkki
2012-01-10
MTRR: get physical address size from CPUID
Sven Schnelle
2011-11-01
Remove XIP_ROM_BASE
Patrick Georgi
2011-10-30
Fix slow CAR execution introduced by 7c7d87182feb78cb2bc02fb3558bef56a41682c9
Rudolf Marek
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