Age | Commit message (Expand) | Author |
2019-09-24 | intel/cpu: Switch older models to TSC_MONOTONIC_TIMER | Kyösti Mälkki |
2019-09-19 | cpu/intel/common: Add CPU_INTEL_COMMON_TIMEBASE | Kyösti Mälkki |
2019-09-10 | AUTHORS: Move src/cpu/intel copyrights into AUTHORS file | Martin Roth |
2019-07-09 | cpu/intel: Drop SMM_TSEG conditional | Kyösti Mälkki |
2019-07-01 | Use 3rdparty/intel-microcode | Arthur Heymans |
2019-03-20 | src: Use 'include <string.h>' when appropriate | Elyes HAOUAS |
2019-01-24 | cpu/intel: Configure IA32_FEATURE_CONTROL for alternative SMRR | Arthur Heymans |
2019-01-23 | nb/intel/i945: Use parallel MP init | Arthur Heymans |
2018-12-20 | cpu/intel/common: decouple IA32_FEATURE_CONTROL lock from set_vmx() | Matt DeVillier |
2018-12-03 | nb/intel/i945: Use common SMM_TSEG code | Arthur Heymans |
2018-10-11 | src: Move common IA-32 MSRs to <cpu/x86/msr.h> | Elyes HAOUAS |
2018-10-05 | src: Fix MSR_PKG_CST_CONFIG_CONTROL register name | Elyes HAOUAS |
2018-06-17 | cpu/intel/car: Remove obsolete files | Kyösti Mälkki |
2017-11-30 | intel: Replace msr(0x198) with msr(IA32_PERF_STATUS) | Elyes HAOUAS |
2017-11-23 | Constify struct cpu_device_id instances | Jonathan Neuschäfer |
2017-06-07 | Use more secure HTTPS URLs for coreboot sites | Paul Menzel |
2017-03-16 | cpu/intel: Wrap lines at 80 columns | Lee Leahy |
2017-03-16 | cpu/intel: Fix the spacing issues | Lee Leahy |
2017-03-16 | cpu/intel: Indent with tabs | Lee Leahy |
2017-03-09 | cpu/intel/model_6{e,f}x: Unify init files | Paul Menzel |
2016-12-27 | cpu/intel/common: Add/Use common function to set virtualization | Matt DeVillier |
2016-12-11 | intel i945 gm45 x4x post-car: Use postcar_frame for MTRR setup | Kyösti Mälkki |
2016-11-11 | intel cache-as-ram: Unify stack setup | Kyösti Mälkki |
2016-10-09 | cpu/intel/model_6ex: Set msr bits for dynamic L2, C2E, C4E | Arthur Heymans |
2016-08-23 | src/cpu: Capitalize CPU, APIC and IOAPIC typo fix | Elyes HAOUAS |
2016-07-31 | src/cpu: Capitalize CPU | Elyes HAOUAS |
2016-07-26 | intel car: Use MTRR WRPROT type for XIP cache | Kyösti Mälkki |
2016-07-22 | intel car: Unify postcodes | Kyösti Mälkki |
2016-07-22 | intel car: Unify whitespace and comment fixes | Kyösti Mälkki |
2016-07-22 | intel car: Remove guard on XIP_ROM_SIZE | Kyösti Mälkki |
2016-06-22 | Ignore RAMTOP for MTRRs | Kyösti Mälkki |
2016-06-22 | intel cache-as-ram: Fix comment about MTRRs | Kyösti Mälkki |
2016-06-21 | intel/model_6ex: Prepare for dynamic CONFIG_RAMTOP | Kyösti Mälkki |
2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
2015-10-15 | cpu/mtrr.h: Fix macro names for MTRR registers | Alexandru Gagniuc |
2015-09-30 | cpu: microcode: Use microcode stored in binary format | Alexandru Gagniuc |
2015-07-07 | x86: Drop -Wa,--divide | Stefan Reinauer |
2015-06-08 | Remove empty lines at end of file | Elyes HAOUAS |
2015-05-21 | Remove address from GPLv2 headers | Patrick Georgi |
2015-05-05 | 3rdparty: move to 3rdparty/blobs | Patrick Georgi |
2015-05-05 | 3rdparty: Move to blobs | Patrick Georgi |
2015-02-28 | cpu/intel: (non-FSP) Remove microcode updates from tree | Alexandru Gagniuc |
2015-02-28 | cpu/intel (non-FSP): Use microcode from blobs repository | Alexandru Gagniuc |
2015-01-27 | vboot2: add verstage | Stefan Reinauer |
2014-10-27 | {arch,cpu,drivers,ec}: Don't hide pointers behind typedefs | Edward O'Callaghan |
2014-10-19 | x86 romstage: Move stack just below RAMTOP | Kyösti Mälkki |
2014-07-08 | cpu: Trivial - drop trailing blank lines at EOF | Edward O'Callaghan |
2014-05-06 | Introduce stage-specific architecture for coreboot | Furquan Shaikh |
2014-05-03 | Move ARCH_* from board/Kconfig to cpu or soc Kconfig. | Furquan Shaikh |
2014-02-12 | PCI: Drop includes under cpu | Kyösti Mälkki |