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path: root/src/cpu/intel/slot_1/Makefile.inc
AgeCommit message (Expand)Author
2018-06-17nb/intel/i440bx: Switch to POSTCAR_STAGEKyösti Mälkki
2018-06-17cpu/intel/slot_1: Switch to different CAR setupKyösti Mälkki
2016-11-08intel post-car: Split legacy socketsKyösti Mälkki
2016-06-21intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-09-04x86: remove cpu_incs as romstage Make variableAaron Durbin
2015-05-21Remove address from GPLv2 headersPatrick Georgi
2014-07-17cpu,Makefile.inc: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
2011-08-04cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.Keith Hui
2010-10-16Move support for Deschutes Slot 1 CPUs (model_65x) into its own directory.Keith Hui
2010-10-13Move out Katmai Slot 1 CPUs (model_67x) from model_6xx to model_67x.Keith Hui
2010-10-12Add missing include of model_6bx for slot_1.Keith Hui
2010-10-06Convert all Intel 440BX boards to Cache-as-RAM (CAR).Uwe Hermann
2010-09-30Rename build system variables to be more intuitive, andPatrick Georgi
2010-03-05Add proper Slot 1 CPU support code/infrastructure.Keith Hui