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path: root/src/cpu/intel/slot_1
AgeCommit message (Expand)Author
2019-11-05intel/i440bx: Switch to UDELAY_TSC and TSC_MONOTONIC_TIMERKyösti Mälkki
2019-11-03cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATEKyösti Mälkki
2019-09-10AUTHORS: Move src/cpu/intel copyrights into AUTHORS fileMartin Roth
2019-07-09arch/x86: Flip HAVE_MONOTONIC_TIMER defaultKyösti Mälkki
2019-07-09cpu/x86: Flip SMM_TSEG defaultKyösti Mälkki
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
2018-06-17nb/intel/i440bx: Switch to POSTCAR_STAGEKyösti Mälkki
2018-06-17cpu/intel/slot_1: Switch to different CAR setupKyösti Mälkki
2018-06-01src/cpu: Remove unneeded includesElyes HAOUAS
2017-09-12cpu/intel/slot_1: Increase CAR size to 8KiBKeith Hui
2017-03-16cpu/intel: Wrap lines at 80 columnsLee Leahy
2017-03-16cpu/intel: Fix brace issues detected by checkpatch.plLee Leahy
2017-03-16cpu/intel: Fix the spacing issuesLee Leahy
2017-03-16cpu/intel: Indent with tabsLee Leahy
2016-11-08intel post-car: Split legacy socketsKyösti Mälkki
2016-08-01Remove non-ascii & unprintable charactersMartin Roth
2016-06-21intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-09-04x86: remove cpu_incs as romstage Make variableAaron Durbin
2015-05-21Remove address from GPLv2 headersPatrick Georgi
2014-12-30intel CAR: Fix DCACHE_RAM_BASE for old socketsKyösti Mälkki
2014-07-17cpu,Makefile.inc: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
2014-07-08cpu: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
2014-07-05Drop redundant select CACHE_AS_RAMKyösti Mälkki
2014-01-16cpu/intel: Make all Intel CPUs load microcode from CBFSAlexandru Gagniuc
2013-07-11cpu: Fix spellingMartin Roth
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
2012-10-07Remove chip.h files without config structureKyösti Mälkki
2012-08-22Auto-declare chip_operationsKyösti Mälkki
2011-08-04cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.Keith Hui
2010-10-16Move support for Deschutes Slot 1 CPUs (model_65x) into its own directory.Keith Hui
2010-10-15Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets.Uwe Hermann
2010-10-13Move out Katmai Slot 1 CPUs (model_67x) from model_6xx to model_67x.Keith Hui
2010-10-12Add missing include of model_6bx for slot_1.Keith Hui
2010-10-06Convert all Intel 440BX boards to Cache-as-RAM (CAR).Uwe Hermann
2010-09-30Rename build system variables to be more intuitive, andPatrick Georgi
2010-05-14license header fixes Nils Jacobs
2010-03-05Add proper Slot 1 CPU support code/infrastructure.Keith Hui
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