coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2018-06-05	nb/intel/i945: Switch to POSTCAR_STAGE	Arthur Heymans
2018-06-02	cpu/intel/car: Prepare for some POSTCAR_STAGE support	Kyösti Mälkki
2016-12-18	intel cache-as-ram: Move DCACHE_RAM_BASE	Kyösti Mälkki
2016-07-22	intel model_106cx: Include CAR from socket directory	Kyösti Mälkki
2015-05-04	cpu: get rid of socket source code	Stefan Reinauer
2014-07-17	cpu,Makefile.inc: Trivial - drop trailing blank lines at EOF	Edward O'Callaghan
2014-07-05	Drop redundant select CACHE_AS_RAM	Kyösti Mälkki
2013-03-01	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel
2012-10-07	Remove chip.h files without config structure	Kyösti Mälkki
2012-08-22	Auto-declare chip_operations	Kyösti Mälkki
2011-01-27	oops. this is weird. CAR addresses should be specified in the socket and not in	Stefan Reinauer
2010-09-30	Rename build system variables to be more intuitive, and	Patrick Georgi
2010-09-27	This patch moves one of the CAR configs to the socket from the single	Warren Turkal
2010-02-07	newconfig is no more.	Patrick Georgi
2010-01-18	Move all IOAPIC selection to southbridges, and remove them	Patrick Georgi
2009-11-04	Fix up typo in Socket 441 CPUs, and add a few (trivial) Kconfig files for them.	Stefan Reinauer
2009-10-28	Add some missing license headers, consistency fixes for others (trivial).	Uwe Hermann
2009-10-28	preliminary Intel D945GCLF Atom+i945 support.	Stefan Reinauer