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path: root/src/cpu/intel
AgeCommit message (Expand)Author
2021-01-06cpu/intel/model_206ax: Simplify C-state acpigenAngel Pons
2021-01-06cpu/intel/model_206ax: Rename `cX_acpower` optionsAngel Pons
2021-01-06cpu/intel/model_206ax: Unify ACPI C-state optionsAngel Pons
2021-01-06cpu/intel/x/chip.h: Drop unused `disable_acpi` settingAngel Pons
2020-12-25cpu/intel/model_206ax: Add more CPU steppingsAngel Pons
2020-12-25nb/intel/sandybridge: Move steppings to CPU headerAngel Pons
2020-12-14arch/x86: Combine bootblock linker scriptsKyösti Mälkki
2020-12-12nb/intel/sandybridge: Clean up stepping logicAngel Pons
2020-12-11Drop many cases of .previous directive useKyösti Mälkki
2020-12-02cbfs: Simplify load/map API names, remove type argumentsJulius Werner
2020-12-01cpu/intel/microcode: Mark assemblycode as 32bitPatrick Rudolph
2020-11-27Makefile.inc: Move adding mcu FIT entriesArthur Heymans
2020-11-22cpu/intel/common: Fill cpu voltage in SMBIOS tablesPatrick Rudolph
2020-11-21intel/socket_441: Increase bootblock sizeJulius Werner
2020-11-10cpu/x86/mtrr.h: Rename CORE2 alternative SMRR registersArthur Heymans
2020-11-10sec/intel/cbnt: Stitch in ACMs in the coreboot imageArthur Heymans
2020-11-09cpu/intel/model_206ax: Get CPU frequencies for SMBIOS type 4Michał Żygowski
2020-11-03cpu/intel/haswell: Move smmrelocate.c MSR definitions to headerAngel Pons
2020-11-02cpu/intel/car/non-evict/cache_as_ram.S: Add support for longmodePatrick Rudolph
2020-10-31{cpu,nb}/intel/haswell: Drop unnecessary `UL` suffixAngel Pons
2020-10-31cpu/intel/common: correct MSR for the Nominal Performance in CPPCMichael Niewöhner
2020-10-30cpu/intel/Makefile.inc: Use correct Kconfig symbolsAngel Pons
2020-10-26cpu/intel/common: implement the two missing CPPC v2 autonomous registersMichael Niewöhner
2020-10-24cpu/intel/common: rework code previously moved to common cpu codeMichael Niewöhner
2020-10-24{cpu,soc}/intel: deduplicate cpu codeMichael Niewöhner
2020-10-23haswell/broadwell: Fix typos of `BCLK`Angel Pons
2020-10-21cpu/intel/common: Fix regressionPatrick Rudolph
2020-10-21{cpu,soc}/intel: replace AES-NI locking by common implemenation callMichael Niewöhner
2020-10-20cpu/intel/model_{2065x,206ax}: fix AES-NI lockingMichael Niewöhner
2020-10-19cpu/intel/common: add a Kconfig to control AES-NI lockingMichael Niewöhner
2020-10-19cpu/intel/common: only lock AES-NI when supportedMichael Niewöhner
2020-10-19cpu/intel/common: rework AES-NI lockingMichael Niewöhner
2020-10-19soc/intel/skl,cpu/intel: copy AES-NI locking to common cpu codeMichael Niewöhner
2020-10-17cpu/intel,soc/intel: drop Kconfig for hyperthreadingMichael Niewöhner
2020-10-16include/cpu/x86: introduce new helper for (un)setting MSRsMichael Niewöhner
2020-10-14haswell/lynxpoint: Align cosmetics with BroadwellAngel Pons
2020-10-02drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES configShelley Chen
2020-09-28cpu/intel/206ax/acpi.c: Fix get_cores_per_packageEvgeny Zinoviev
2020-09-27cpu/intel/haswell/smmrelocate.c: Spell `CPU` in uppercaseAngel Pons
2020-09-27cpu/intel/haswell/haswell_init.c: Align printk's with BroadwellAngel Pons
2020-09-26arch/x86: Introduce `ARCH_ALL_STAGES_X86_32`Angel Pons
2020-09-21src/cpu: Drop unneeded empty linesElyes HAOUAS
2020-09-12cpu/intel/model_1067x: enable PECIMichael Büchler
2020-08-30cpu/intel/haswell: Set LT_LOCK_MEMORY MSR on finalize stepAngel Pons
2020-08-21cpu/intel/haswell: Select HAVE_ASAN_IN_ROMSTAGEHarshit Sharma
2020-08-18cpu/intel/common: Use macro for access_sizeElyes HAOUAS
2020-08-17cpu/intel/model_6fx: Include Conroe-L microcodeArthur Heymans
2020-08-11cpu/intel: Remove Core 2 Duo E8200 CPUID from model_6fxAngel Pons
2020-08-06cpu/intel/common: Add `intel_ht_supported` functionAngel Pons
2020-08-03cpu/intel/haswell: add Crystal Well CPU IDsIru Cai
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