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path: root/src/cpu/intel
AgeCommit message (Expand)Author
2014-07-08cpu: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
2014-07-05Drop redundant select CACHE_AS_RAMKyösti Mälkki
2014-07-05intel: Make monotonic timer a first class citizenEdward O'Callaghan
2014-06-17intel/model_2065x: Add 20652 microcode.Vladimir Serbinenko
2014-05-30cpu/intel/fsp_model_206ax: change realpath to readlinkMartin Roth
2014-05-17build: separate CPPFLAGS from CFLAGSPatrick Georgi
2014-05-17build: CPPFLAGS is more common than INCLUDESPatrick Georgi
2014-05-13cpu/intel: Add CPU socket rPGA988BZaolin
2014-05-10Replace SERIAL_CPU_INIT with PARALLEL_CPU_INITKyösti Mälkki
2014-05-09cougar_canyon2: Switch CPU/NB/SB to the shared FSP codeMartin Roth
2014-05-06Introduce stage-specific architecture for corebootFurquan Shaikh
2014-05-05haswell: move to mp_init libraryAaron Durbin
2014-05-03Move ARCH_* from board/Kconfig to cpu or soc Kconfig.Furquan Shaikh
2014-04-26Rename coreboot_ram stage to ramstageFurquan Shaikh
2014-04-26Get rid of HAVE_INIT_TIMER config optionFurquan Shaikh
2014-03-20rmodules: use rmodtool to create rmodulesAaron Durbin
2014-03-16Make POST device configurable.Idwer Vollering
2014-02-25Remove CACHE_ROM.Vladimir Serbinenko
2014-02-20intel/model_2065x: Fix APICID generation.Vladimir Serbinenko
2014-02-16haswell: backup the default SMM region on resumeAaron Durbin
2014-02-15coreboot: infrastructure for different ramstage loadersAaron Durbin
2014-02-12PCI: Drop includes under cpuKyösti Mälkki
2014-02-06usbdebug: Drop obsolete codeKyösti Mälkki
2014-02-01cpu/intel/model_2065x: Add model 20652Vladimir Serbinenko
2014-01-30cpu/intel: allow non-packaged scoped turbo settingAaron Durbin
2014-01-30coreboot: config to cache ramstage outside CBMEMAaron Durbin
2014-01-30vboot: provide empty vboot_verify_firmware()Aaron Durbin
2014-01-28intel: fix microcode compilation failure in bootblockAaron Durbin
2014-01-26src/cpu: Fix spelling of MTTR to MTRRPaul Menzel
2014-01-23intel/microcode: Remove leftover MICROCODE_INCLUDE_PATH.Vladimir Serbinenko
2014-01-16cpu/intel: Remove dummy terminators from microcode blobsAlexandru Gagniuc
2014-01-16cpu/intel: Make all Intel CPUs load microcode from CBFSAlexandru Gagniuc
2014-01-15nehalem/sandy/ivy/haswell: Enable WRPROT cache for all of flashKyösti Mälkki
2014-01-15Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRRKyösti Mälkki
2014-01-11intel/fsp: Fix microcode includingPatrick Georgi
2013-12-21haswell: Update microcode revisionDuncan Laurie
2013-12-17cpu/intel: Do not rely on CBFS microcode having a terminatorAlexandru Gagniuc
2013-12-13cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFSAlexandru Gagniuc
2013-12-12haswell: Export functions for CPU family+model and steppingDuncan Laurie
2013-12-12haswell: Update ULT microcode to rev 14hDuncan Laurie
2013-12-07haswell: VR controller configurationAaron Durbin
2013-12-07haswell: Misc power management setup and fixesDuncan Laurie
2013-12-05cpu: Remove BOARD_MICROCODE_CBFS_GENERATE Kconfig optionAlexandru Gagniuc
2013-12-04Add the Intel FSP 206ax CPU core supportMarc Jones
2013-12-01slippy/falco/peppy: Fix SPD GPIO initialization.Aaron Durbin
2013-11-25haswell: check for clean resetAaron Durbin
2013-11-24haswell: Update ULT microcode to 0x10Duncan Laurie
2013-11-24haswell: Remove limit on package C-stateDuncan Laurie
2013-11-24haswell: split microcode between ULT and non-ULTAaron Durbin
2013-11-24haswell: Update ULT microcode to rev 'a'Duncan Laurie
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