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path: root/src/cpu/intel
AgeCommit message (Expand)Author
2012-05-02Don't include console.h in microcode.c when compiling with ROMCCStefan Reinauer
2012-04-30Fix up Sandybridge C state generation codeStefan Reinauer
2012-04-30Rework ACPI CST table generationStefan Reinauer
2012-04-26microcode: print date of microcode and unify outputStefan Reinauer
2012-04-26Revamp Intel microcode update codeStefan Reinauer
2012-04-25Replace cache control magic numbers with symbolsPatrick Georgi
2012-04-06Fix support for RAM-less multi-processor initKyösti Mälkki
2012-04-05Add support for Intel Sandybridge CPUStefan Reinauer
2012-04-03Add support for Intel Turbo Boost featureStefan Reinauer
2012-04-02Apply cache-as-ram conditionally on socket mPGA604Kyösti Mälkki
2012-03-31Whitespace fixesPatrick Georgi
2012-03-31Intel cpus: get MAXPHYADDR at runtime for new CARKyösti Mälkki
2012-03-31Intel cpus: add hyper-threading CPU support to new CARKyösti Mälkki
2012-03-31Intel cpus: improve CPU compatibility of new CARKyösti Mälkki
2012-03-31Intel cpus: apply some good programming practices in new CARKyösti Mälkki
2012-03-31Intel cpus: cache actual size of the Flash ROM deviceKyösti Mälkki
2012-03-31Intel cpus: copy model_6ex CAR codeKyösti Mälkki
2012-03-25Intel cpus: Fix deadlock on hyper-threading initKyösti Mälkki
2012-03-17Intel cpus: Include CAR from socketKyösti Mälkki
2012-02-16Intel cpus: use CPU_PHYSMASK_HI define in CARKyösti Mälkki
2012-02-15Intel model_106cx: Use symbolic names for MTRR bitsKyösti Mälkki
2012-02-10Intel cpus: apply un-written naming rulesKyösti Mälkki
2012-02-09Add Intel Socket LGA771Sven Schnelle
2012-01-10MTRR: get physical address size from CPUIDSven Schnelle
2012-01-09ACPI: mark empty get_cst_entries() weakSven Schnelle
2011-11-01Remove XIP_ROM_BASEPatrick Georgi
2011-10-30Fix slow CAR execution introduced by 7c7d87182feb78cb2bc02fb3558bef56a41682c9Rudolf Marek
2011-10-28Get rid of the old romstage-as-bootblock ROM layoutPatrick Georgi
2011-10-28Get rid of AUTO_XIP_ROM_BASEPatrick Georgi
2011-10-25SPEEDSTEP: write _CST tablesSven Schnelle
2011-10-18Activate older Xeon P4 microcodesKyösti Mälkki
2011-09-09Crank up CPU speed on Intel Core and Core2 CPUsPatrick Georgi
2011-08-04cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.Keith Hui
2011-05-03Enable caching for ROM area in model_6ex/cache_as_ram.incSven Schnelle
2011-04-21more ifdef -> if fixesStefan Reinauer
2011-04-14Use symbolic names for some MTRR bits instead of numbers in CAR codeStefan Reinauer
2011-04-11Unify use of post_codeAlexandru Gagniuc
2011-01-27oops. this is weird. CAR addresses should be specified in the socket and not inStefan Reinauer
2011-01-19Revert r5902 to make code more readable again. At least three people like toStefan Reinauer
2011-01-12drop unused filesStefan Reinauer
2010-12-12fix model 106cxStefan Reinauer
2010-12-11factor out cpu power management base into a separate file. And fix a bug inStefan Reinauer
2010-12-08These empty files sneaked in from another patch and shouldn't have been inclu...Tobias Diedrich
2010-12-08Tobias Diedrich wrote:Tobias Diedrich
2010-12-08Move "select CACHE_AS_RAM" lines from boards into CPU socket.Uwe Hermann
2010-11-17Move Intel power management related defines to some central location.Patrick Georgi
2010-10-18update intel microcode files.Stefan Reinauer
2010-10-18Make update-microcodes.sh executable.Uwe Hermann
2010-10-17update intel microcode update scriptStefan Reinauer
2010-10-17Removes model_65x CPUIDs from model_6xx code.Keith Hui
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