coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2021-01-06	cpu/intel/x/chip.h: Drop unused `disable_acpi` setting	Angel Pons
2020-12-25	cpu/intel/model_206ax: Add more CPU steppings	Angel Pons
2020-12-25	nb/intel/sandybridge: Move steppings to CPU header	Angel Pons
2020-12-14	arch/x86: Combine bootblock linker scripts	Kyösti Mälkki
2020-12-12	nb/intel/sandybridge: Clean up stepping logic	Angel Pons
2020-12-11	Drop many cases of .previous directive use	Kyösti Mälkki
2020-12-02	cbfs: Simplify load/map API names, remove type arguments	Julius Werner
2020-12-01	cpu/intel/microcode: Mark assemblycode as 32bit	Patrick Rudolph
2020-11-27	Makefile.inc: Move adding mcu FIT entries	Arthur Heymans
2020-11-22	cpu/intel/common: Fill cpu voltage in SMBIOS tables	Patrick Rudolph
2020-11-21	intel/socket_441: Increase bootblock size	Julius Werner
2020-11-10	cpu/x86/mtrr.h: Rename CORE2 alternative SMRR registers	Arthur Heymans
2020-11-10	sec/intel/cbnt: Stitch in ACMs in the coreboot image	Arthur Heymans
2020-11-09	cpu/intel/model_206ax: Get CPU frequencies for SMBIOS type 4	Michał Żygowski
2020-11-03	cpu/intel/haswell: Move smmrelocate.c MSR definitions to header	Angel Pons
2020-11-02	cpu/intel/car/non-evict/cache_as_ram.S: Add support for longmode	Patrick Rudolph
2020-10-31	{cpu,nb}/intel/haswell: Drop unnecessary `UL` suffix	Angel Pons
2020-10-31	cpu/intel/common: correct MSR for the Nominal Performance in CPPC	Michael Niewöhner
2020-10-30	cpu/intel/Makefile.inc: Use correct Kconfig symbols	Angel Pons
2020-10-26	cpu/intel/common: implement the two missing CPPC v2 autonomous registers	Michael Niewöhner
2020-10-24	cpu/intel/common: rework code previously moved to common cpu code	Michael Niewöhner
2020-10-24	{cpu,soc}/intel: deduplicate cpu code	Michael Niewöhner
2020-10-23	haswell/broadwell: Fix typos of `BCLK`	Angel Pons
2020-10-21	cpu/intel/common: Fix regression	Patrick Rudolph
2020-10-21	{cpu,soc}/intel: replace AES-NI locking by common implemenation call	Michael Niewöhner
2020-10-20	cpu/intel/model_{2065x,206ax}: fix AES-NI locking	Michael Niewöhner
2020-10-19	cpu/intel/common: add a Kconfig to control AES-NI locking	Michael Niewöhner
2020-10-19	cpu/intel/common: only lock AES-NI when supported	Michael Niewöhner
2020-10-19	cpu/intel/common: rework AES-NI locking	Michael Niewöhner
2020-10-19	soc/intel/skl,cpu/intel: copy AES-NI locking to common cpu code	Michael Niewöhner
2020-10-17	cpu/intel,soc/intel: drop Kconfig for hyperthreading	Michael Niewöhner
2020-10-16	include/cpu/x86: introduce new helper for (un)setting MSRs	Michael Niewöhner
2020-10-14	haswell/lynxpoint: Align cosmetics with Broadwell	Angel Pons
2020-10-02	drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config	Shelley Chen
2020-09-28	cpu/intel/206ax/acpi.c: Fix get_cores_per_package	Evgeny Zinoviev
2020-09-27	cpu/intel/haswell/smmrelocate.c: Spell `CPU` in uppercase	Angel Pons
2020-09-27	cpu/intel/haswell/haswell_init.c: Align printk's with Broadwell	Angel Pons
2020-09-26	arch/x86: Introduce `ARCH_ALL_STAGES_X86_32`	Angel Pons
2020-09-21	src/cpu: Drop unneeded empty lines	Elyes HAOUAS
2020-09-12	cpu/intel/model_1067x: enable PECI	Michael Büchler
2020-08-30	cpu/intel/haswell: Set LT_LOCK_MEMORY MSR on finalize step	Angel Pons
2020-08-21	cpu/intel/haswell: Select HAVE_ASAN_IN_ROMSTAGE	Harshit Sharma
2020-08-18	cpu/intel/common: Use macro for access_size	Elyes HAOUAS
2020-08-17	cpu/intel/model_6fx: Include Conroe-L microcode	Arthur Heymans
2020-08-11	cpu/intel: Remove Core 2 Duo E8200 CPUID from model_6fx	Angel Pons
2020-08-06	cpu/intel/common: Add `intel_ht_supported` function	Angel Pons
2020-08-03	cpu/intel/haswell: add Crystal Well CPU IDs	Iru Cai
2020-08-03	cpu/intel/common/fsb.c: add Crystal Well support	Iru Cai
2020-07-26	cpu/intel/car/romstage.c: Remove unused <bootblock_common.h>	Elyes HAOUAS
2020-07-26	src: Change BOOL CONFIG_ to CONFIG() in comments & strings	Martin Roth