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2020-11-27Makefile.inc: Move adding mcu FIT entriesArthur Heymans
This can be done using in the INTERMEDIATE target in the proper place. Change-Id: I28a7764205e0510be89c131058ec56861a479699 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46453 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22cpu/intel/common: Fill cpu voltage in SMBIOS tablesPatrick Rudolph
Introduce a weak function to let the platform code provide the processor voltage in 100mV units. Implement the function on Intel platforms using the MSR_PERF_STATUS msr. On other platforms the processor voltage still reads as unknown. Tested on Intel CFL. The CPU voltage is correctly advertised. Change-Id: I31a7efcbeede50d986a1c096a4a59a316e09f825 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-21intel/socket_441: Increase bootblock sizeJulius Werner
One mainboard using this socket has less than 20 bytes of space left in its bootblock, hindering development. Double the bootblock size to solve the problem. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I620c13eab53c3326a4f4660b63ed1dd0fc81f563 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47585 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-10cpu/x86/mtrr.h: Rename CORE2 alternative SMRR registersArthur Heymans
It is too easy to confuse those with IA32_SMRR_PHYS_x registers. Change-Id: Ice02ab6c0315a2be14ef110ede506262e3c0a4d5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46896 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-10sec/intel/cbnt: Stitch in ACMs in the coreboot imageArthur Heymans
Actual support CBnT will be added later on. Change-Id: Icc35c5e6c74d002efee43cc05ecc8023e00631e0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46456 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09cpu/intel/model_206ax: Get CPU frequencies for SMBIOS type 4Michał Żygowski
Calculate the frequencies based on the appropriate MSRs and pass them to SMBIOS tables generator. Ivybridge microarchitecture does not yet implement CPUID 16H leaf used to obtain the required frequencies. TEST=Intel Core i7-3770, TianoCore UEFI payload displays the CPU frequency correctly equal 3.4GHz in Boot Manager Menu, dmidecode shows correct frequencies according to Intel ARK, 3.4GHz base and 3.9GHz turbo Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iefbae6111d39107eacac7e61654311646c6981eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/47058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-03cpu/intel/haswell: Move smmrelocate.c MSR definitions to headerAngel Pons
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change. Change-Id: Ia271718477ea227b9ba7e836b0abe02264778129 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46733 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02cpu/intel/car/non-evict/cache_as_ram.S: Add support for longmodePatrick Rudolph
* Use heap for linker script calculated constant to fix relocation symbols in mixed assembly code. Tested on HPZ220: * Still boots in x86_32. Tested on Lenovo T410: * Doesn't need the MMX register fix in long mode. Change-Id: I3e72a0bebf728fb678308006ea3a3aeb92910a84 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-31{cpu,nb}/intel/haswell: Drop unnecessary `UL` suffixAngel Pons
Tested with BUILD_TIMELESS=1, Google Wolf does not change. Change-Id: I029ab0dccbf7b61d641cccf79b491fabf97ab74a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46720 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-31cpu/intel/common: correct MSR for the Nominal Performance in CPPCMichael Niewöhner
The "Nominal Performance" is not the same as the "Guaranteed Performance", but is defined as the performance a processor can deliver continously under ideal environmental conditions. According to edk2, this is the "Maximum Non-Turbo Ratio", which needs to be read from MSR_PLATFORM_INFO instead of IA32_HWP_CAPABILITIES. Correct the entry in the CPPC package. Test: dumped SSDT from Supermicro X11SSM-F and checked decompiled version Change-Id: Ic2c27fd3e14af18aa4101c0acd7a5ede15d1f3a9 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46464 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30cpu/intel/Makefile.inc: Use correct Kconfig symbolsAngel Pons
Guard CPU code using CPU Kconfig symbols instead of northbridge symbols. Change-Id: I0e5d7fc2e042381b96d2fbdfa34a3d4bf58201f9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46943 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26cpu/intel/common: implement the two missing CPPC v2 autonomous registersMichael Niewöhner
This implements the two missing registers for the CPPC Hardware Autonomous mode (HWP) to the CPPC v2 package. The right values can be determined via Intel SDM and the ACPI 6.3 spec. Test: dumped SSDT from Supermicro X11SSM-F and checked decompiled version Change-Id: I7e2f4e4ae6a0fdb57204538bd62ead97cb540e91 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Matt Delco <delco@chromium.org>
2020-10-24cpu/intel/common: rework code previously moved to common cpu codeMichael Niewöhner
Rework the code moved to common code in CB:46274. This involves simplification by using appropriate helpers for MSR and CPUID, using macros instead of plain values for MSRs and cpu features and adding documentation to the header. Change-Id: I7615fc26625c44931577216ea42f0a733b99e131 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-24{cpu,soc}/intel: deduplicate cpu codeMichael Niewöhner
Move a whole bunch of copy-pasta code from soc/intel/{bdw,skl,cnl,icl, tgl,ehl,jsl,adl} and cpu/intel/{hsw,model_*} to cpu/intel/common. This change just moves the code. Rework is done in CB:46588. Change-Id: Ib0cc834de8492d59c423317598e1c11847a0b1ab Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46274 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23haswell/broadwell: Fix typos of `BCLK`Angel Pons
Change-Id: Ifed3c8250d5c9869493285d0b87580b70ff37965 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-10-21cpu/intel/common: Fix regressionPatrick Rudolph
Fix the logic introduced in CB:46276 "cpu/intel/common: only lock AES-NI when supported" which needs to be negated. Change-Id: Icaf882625529842ea0aedf39147fc9a9e6081e43 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46634 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21{cpu,soc}/intel: replace AES-NI locking by common implemenation callMichael Niewöhner
Deduplicate code by using the new common cpu code implementation of AES-NI locking. Change-Id: I7ab2d3839ecb758335ef8cc6a0c0c7103db0fa50 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-20cpu/intel/model_{2065x,206ax}: fix AES-NI lockingMichael Niewöhner
MSR_FEATURE_CONFIG, which is used for locking AES-NI, is core-scoped, not package-scoped. Thus, move locking from SMM to core init, where the code gets executed once per core. Change-Id: I3a6f7fc95ce226ce4246b65070726087eb9d689c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-19cpu/intel/common: add a Kconfig to control AES-NI lockingMichael Niewöhner
Add a Kconfig to be able to disable locking of AES-NI for e.g debugging, testing, ... Change-Id: I4eaf8d7d187188ee6e78741b1ceb837c40c2c402 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-19cpu/intel/common: only lock AES-NI when supportedMichael Niewöhner
Add a check to only lock AES-NI when AES is supported. Change-Id: Ia7ffd5393a3e972f461ff7991b9c5bd363712361 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-19cpu/intel/common: rework AES-NI lockingMichael Niewöhner
Simplify the AES-NI code by using msr_set and correct the comment. Change-Id: Ib2cda433bbec0192277839c02a1862b8f41340cb Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-19soc/intel/skl,cpu/intel: copy AES-NI locking to common cpu codeMichael Niewöhner
Copy the AES-NI locking function to common cpu code to be able to reuse it. This change only copies the code and adds the MSR header file. Any further rework and later deduplication on the platforms code is done in the follow-up changes. Change-Id: I81ad5c0d4797b139435c57d3af0a95db94a5c15e Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-17cpu/intel,soc/intel: drop Kconfig for hyperthreadingMichael Niewöhner
Drop the Kconfig for hyperthreading to be always able to check at runtime if hyperthreading is supported. Having a Kconfig for this doesn't have any benefit. Change-Id: Ib7b7a437d758f7fe4a09738db1eab8189290b288 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-16include/cpu/x86: introduce new helper for (un)setting MSRsMichael Niewöhner
msr_set_bit can only set single bits in MSRs and causes mixing of bit positions and bitmasks in the MSR header files. Thus, replace the helper by versions which can unset and set whole MSR bitmasks, just like the "and-or"-helper, but in the way commit 64a6b6c was done (inversion done in the helper). This helps keeping the MSR macros unified in bitmask style. In sum, the three helpers msr_set, msr_unset and msr_unset_and_set get added. The few uses of msr_set_bit have been replaced by the new version, while the used macros have been converted accordingly. Change-Id: Idfe9b66e7cfe78ec295a44a2a193f530349f7689 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46354 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14haswell/lynxpoint: Align cosmetics with BroadwellAngel Pons
Tested with BUILD_TIMELESS=1, Google Wolf does not change. Change-Id: Ibd8430352e860ffc0e2030fd7bc73582982f4695 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45698 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-02drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES configShelley Chen
Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate older x86 platforms that don't allow writing to SPI flash when early stages are running XIP from flash. If BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is not selected, BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY will get auto-selected if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y. This allows for current platforms that write to flash in the earlier stages, assuming that they have that capability. BUG=b:150502246 BRANCH=None TEST=diff the coreboot.rom files resulting from running ./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a --timeless with and without this change to make sure that there was no difference. Also did this for GOOGLE_CANDY board, which is baytrail based (and has BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES enabled). Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-28cpu/intel/206ax/acpi.c: Fix get_cores_per_packageEvgeny Zinoviev
Current implementation uses CPUID 0Bh function that returns the number of logical cores of requested level. The problem with this approach is that this value doesn't change when HyperThreading is disabled (it's in the Intel docs), so it breaks generate_cpu_entries(). - Use MSR 0x35 instead, which returns the correct number of logical processors with and without HT. - Rename the function to get_logical_cores_per_package, which is more accurate. Tested on ThinkPad X220 with and without HT. Related to CB:29669. Change-Id: Ib32c2d40408cfa42ca43ab42ed661c168e579ada Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-27cpu/intel/haswell/smmrelocate.c: Spell `CPU` in uppercaseAngel Pons
This is to align Haswell and Broadwell. Change-Id: I8585597a8de164fb8d3b33db0d95c3aaf3cd7afc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45711 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-27cpu/intel/haswell/haswell_init.c: Align printk's with BroadwellAngel Pons
Change-Id: I09f4fc5af28b20663b87d18852d585121feaab09 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-09-26arch/x86: Introduce `ARCH_ALL_STAGES_X86_32`Angel Pons
Nearly every x86 platform uses the same arch for all stages. The only exception is Picasso. So, factor out redundant symbols from the rest. Alder Lake is not yet complete, so it has been skipped for now. Change-Id: I7cff9efbc44546807d9af089292c69fb0acc7bad Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-21src/cpu: Drop unneeded empty linesElyes HAOUAS
Change-Id: I116b15c83fcc5d69d3f80a2e6cf0fb085064d9a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-12cpu/intel/model_1067x: enable PECIMichael Büchler
This is required for Super I/Os to be able to read the CPU temperature through PECI. On 45nm Core 2 CPUs (Wolfdale, Yorkfield) it is not enabled by default. This is probably related to erratum AW67 "Enabling PECI via the PECI_CTL MSR incorrectly writes CPUID_FEATURE_MASK1 MSR". The suggested workaround is "Do not initialize PECI before processor update is loaded". Since coreboot performs microcode updates before running this code it should not cause any trouble. It was tested on a Core 2 Duo E8400, stepping E0. PECI is already enabled by default on older (65nm) CPUs. Tested: Pentium Dual-Core E2160. See commit edac28ce65e48d6b2a0a2421d046a4fe4b2bf589 for the same change on cpu/intel/model_6fx. Signed-off-by: Michael Büchler <michael.buechler@posteo.net> Change-Id: I5a3ec033bd816665af4ecc82f7b167857cd7c1b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-30cpu/intel/haswell: Set LT_LOCK_MEMORY MSR on finalize stepAngel Pons
This is a security lock and is required for TXT, among other things. Tested on Asrock B85M Pro4, still boots. Change-Id: I7b2e8a60ce92cbf523c520be0b365f28413b9624 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44884 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-21cpu/intel/haswell: Select HAVE_ASAN_IN_ROMSTAGEHarshit Sharma
Enable ASan in romstage for haswell as it has been tested on Lenovo ThinkPad T440P. Change-Id: I6eae242c71f41c9159658ae68d61b4036ad42d42 Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-08-18cpu/intel/common: Use macro for access_sizeElyes HAOUAS
Change-Id: I0388ac41403ff03943c91ba19f6527e7d77e0139 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-08-17cpu/intel/model_6fx: Include Conroe-L microcodeArthur Heymans
This CPU variant has a different CPUID signature. Change-Id: Ice2c1b86382e5d91d9eda717e6522ed0a9c2229f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-11cpu/intel: Remove Core 2 Duo E8200 CPUID from model_6fxAngel Pons
With a CPUID of 10676, it is clearly model_1067x... Wait, it's already there, but the comment is wrong. This ID isn't for Core Duo CPUs. Change-Id: Ia4b73537805e2a8fa9e28bde76aa20a524f8f873 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-06cpu/intel/common: Add `intel_ht_supported` functionAngel Pons
Change-Id: I90c0378c4042dec39c8c86c1d2339a5cbcfe78e3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-08-03cpu/intel/haswell: add Crystal Well CPU IDsIru Cai
Change-Id: Ife4ae71fd977d32d7b11ee7e2a1a7e2ec3eec52f Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-03cpu/intel/common/fsb.c: add Crystal Well supportIru Cai
Without this change, there will be no console output when using a Crystal Well CPU. Tested with i5-4570R (with LGA1150 mod) on ASRock H81M-HDS. Change-Id: Id18645c52d9c4a4ea7acb602bcb39b796d9e24b9 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26cpu/intel/car/romstage.c: Remove unused <bootblock_common.h>Elyes HAOUAS
Change-Id: Ib47497cf8576063d42bc4a1dd2cc2e0fc56868d3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26src: Change BOOL CONFIG_ to CONFIG() in comments & stringsMartin Roth
The Kconfig lint tool checks for cases of the code using BOOL type Kconfig options directly instead of with CONFIG() and will print out warnings about it. It gets confused by these references in comments and strings. To fix it so that it can find the real issues, just update these as we would with real issues. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I5c37f0ee103721c97483d07a368c0b813e3f25c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26cpu,soc/intel: Drop select SMPKyösti Mälkki
Implicitly selected with MAX_CPUS != 1. Change-Id: I4ac3e30e9f96cd52244b4bae73bafce0564d41e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26cpu/intel/model_206ax: Clean up includesElyes HAOUAS
Change-Id: I5dc2e7b327278c281087c7461e62569aab3fe450 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26src: Remove unused 'include <cpu/intel/common/common.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <cpu/intel/common/common.h>' -- src/) <(git grep -l 'set_vmx_and_lock\|set_feature_ctrl_vmx\|set_feature_ctrl_lock\|cppc_config\|cpu_init_cppc_config\|intel_ht_sibling' -- src/) |grep '<' Change-Id: I4d749a32aa50fa2f005e8496983013977742a99b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42394 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14cpu/intel/model_1067x: Drop <cpu/x86/mp.h> includeElyes HAOUAS
Found using: diff <(git grep -l 'include <cpu/x86/mp.h>' -- src) <(git grep -l 'CACHELINE_SIZE\|cpu_info\|mfence\|mfence\|mp_ops\|mp_init_with_smm\|MP_RUN_ON_ALL_CPUS\|mp_run_on_aps\|mp_run_on_all_cpus\|mp_park_aps\|smm_initiate_relocation_parallel\|smm_initiate_relocation' -- src/) |grep '<' Change-Id: Ib721e667144d6803261f3761a077570e0e27391d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-14src: Remove unused 'include <cpu/x86/msr.h>'Elyes HAOUAS
Found using: diff <(git grep -l '#include <cpu/x86/msr.h>' -- src/) <(git grep -l 'IA32_EFER\|EFER_\|TSC_MSR\|IA32_\|FEATURE_CONTROL_LOCK_BIT\|FEATURE_ENABLE_VMX\|SMRR_ENABLE\|CPUID_\|SGX_GLOBAL_ENABLE\|PLATFORM_INFO_SET_TDP\|SMBASE_RO_MSR\|MCG_CTL_P\|MCA_BANKS_MASK\|FAST_STRINGS_ENABLE_BIT\|SPEED_STEP_ENABLE_BIT\|ENERGY_POLICY_\|SMRR_PHYSMASK_\|MCA_STATUS_\|VMX_BASIC_HI_DUAL_MONITOR\|MC0_ADDR\|MC0_MISC\|MC0_CTL_MASK\|msr_struct\|msrinit_struct\|soc_msr_read\|soc_msr_write\|rdmsr\|wrmsr\|mca_valid\|mca_over\|mca_uc\|mca_en\|mca_miscv\|mca_addrv\|mca_pcc\|mca_idv\|mca_cecc\|mca_uecc\|mca_defd\|mca_poison\|mca_sublink\|mca_err_code\|mca_err_extcode\|MCA_ERRCODE_\|MCA_BANK_\|MCA_ERRTYPE_\|mca_err_type\|msr_set_bit\|msr_t\|msrinit_t' -- src/) |grep '<' Change-Id: I45a41e77e5269969280e9f95cfc0effe7f117a40 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41969 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14src: Remove unused 'include <types.h>'Elyes HAOUAS
Files found using: diff <(git grep -l '#include <types.h>' -- src/) <(git grep -l 'BIT(\|size_t\|wchar_t\|wint_t\|NULL\|DEVTREE_EARLY\|DEVTREE_CONST\|MAYBE_STATIC_NONZERO\|zeroptr\|int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX\|bool\|true\|false\|cb_err\|CB_SUCCESS\|CB_ERR\|CB_ERR_ARG\|CB_CMOS_\|CB_KBD_\|CB_I2C_\|cb_err_t\|DIV_ROUND_CLOSEST\|container_of\|__unused\|alloca(\|ARRAY_SIZE\|ALIGN\|ALIGN_UP\|ALIGN_DOWN\|IS_ALIGNED\|__CMP_UNSAFE\|MIN_UNSAFE\|MAX_UNSAFE\|__CMP_SAFE\|__CMP\|MIN(\|MAX(\|ABS(\|IS_POWER_OF_2\|POWER_OF_2\|DIV_ROUND_UP\|SWAP(\|KiB\|MiB\|GiB\|KHz\|MHz\|GHz\|offsetof(\|check_member\|member_size' -- src/)|grep -v vendor |grep '<' Change-Id: I5d99d844cc58d80acb505d98da9d3ec76319b2eb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41677 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-10cpu/intel/haswell/finalize.c: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I3fc616eeb975aae7a5937f8b555ae554010d8dd3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-09cpu/intel/model_2065x/model_2065x_init.c: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I16fe12368ce7ffe2fd4d2a5580dd92c19a695848 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-12 01:56:09 +0000