coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2018-11-01	cpu/intel/haswell: Only change the slow ramp rate for ULT CPUs	Tristan Corrick
2018-11-01	cpu/intel/haswell: Allow use of TSC for the monotonic timer	Tristan Corrick
2018-11-01	cpu/intel/haswell: Add the CPUID for Haswell C0 CPUs	Tristan Corrick
2018-10-30	src: Add missing include <stdint.h>	Elyes HAOUAS
2018-10-24	cpu/intel/smm: Don't make assumptions on TSEG_SIZE	Arthur Heymans
2018-10-22	intel: Use CF9 reset (part 1)	Patrick Rudolph
2018-10-11	src: Move common IA-32 MSRs to <cpu/x86/msr.h>	Elyes HAOUAS
2018-10-11	src: Replace MSR addresses with macros	Elyes HAOUAS
2018-10-08	Move compiler.h to commonlib	Nico Huber
2018-10-05	src: Fix MSR_PKG_CST_CONFIG_CONTROL register name	Elyes HAOUAS
2018-10-04	cpu/intel/car: Fix typo	Elyes HAOUAS
2018-09-28	src/*: normalize Google copyright headers	Patrick Georgi
2018-09-26	cpu/intel/model_206ax: detect number of MCE banks	Dan Elkouby
2018-09-18	cpu/*/car: fix ancient URL explaining XIP range run-time calculation	Stefan Tauner
2018-08-20	cpu/intel/common: add function to init cppc_config	Matt Delco
2018-08-17	intel/socket_mPGA604: Keep only model f2x	Kyösti Mälkki
2018-08-13	src: Get rid of non-local header treated as local	Elyes HAOUAS
2018-08-13	cpu/intel/car: Align the stack to 16 bytes before romstage_main	Arthur Heymans
2018-08-09	src/cpu: Fix typo	Elyes HAOUAS
2018-08-09	cpu/intel/smm: Make sure SMRR base is aligned to SMRR size	Arthur Heymans
2018-07-30	nb/intel/gm45: Use common code for SMM in TSEG	Arthur Heymans
2018-07-30	cpu/intel/smm/gen1: Use correct MSR for model_6fx and model_1067x	Arthur Heymans
2018-07-30	cpu/intel/microcode: Add helper functions to get microcode info	Rizwan Qureshi
2018-07-28	nb/intel/sandybridge: Move CPU report to cpu folder	Patrick Rudolph
2018-07-28	intel/sandybridge: Don't hardcode platform type	Patrick Rudolph
2018-07-25	drivers/tpm: Add TPM ramstage driver for devices without vboot.	Philipp Deppenwiese
2018-07-24	cpu/x86/mtrr.h: Rename MSR SMRR_PHYS_x to IA32_SMRR_PHYSx	Arthur Heymans
2018-07-09	src/{arch,commonlib,cpu}: Use "foo bar" instead of "foo bar"	Elyes HAOUAS
2018-06-27	cpu/intel/p4-netburst: skip caching rom on model_fxx	Arthur Heymans
2018-06-27	x86/car: Replace reference of copy_and_run location	Kyösti Mälkki
2018-06-21	Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location"	Arthur Heymans
2018-06-17	nb/intel/i440bx: Switch to POSTCAR_STAGE	Kyösti Mälkki
2018-06-17	cpu/intel/car/p3: Use variable MTRR count	Kyösti Mälkki
2018-06-17	cpu/intel/slot_1: Switch to different CAR setup	Kyösti Mälkki
2018-06-17	cpu/intel/car: Remove obsolete files	Kyösti Mälkki
2018-06-14	cpu/intel/haswell: Use the common intel romstage_main function	Arthur Heymans
2018-06-06	arch/x86: Make RELOCATABLE_RAMSTAGE the default	Kyösti Mälkki
2018-06-06	cpu/intel/model_{6xx,f2x,f3x,f4x}: Remove unneeded include	Elyes HAOUAS
2018-06-05	cpu/intel/haswell: Switch to POSTCAR_STAGE	Arthur Heymans
2018-06-05	cpu/intel/model_2065x: Switch to POSTCAR_STAGE	Arthur Heymans
2018-06-05	cpu/intel/model_206ax: Switch to POSTCAR_STAGE	Arthur Heymans
2018-06-05	cpu/intel/car/non-evict: Improve a few things	Arthur Heymans
2018-06-05	cpu/intel/car/non-evict: Prepare for some POSTCAR_STAGE support	Arthur Heymans
2018-06-05	nb/intel/gm45: Switch to POSTCAR_STAGE	Arthur Heymans
2018-06-05	nb/intel/x4x: Switch to POSTCAR_STAGE	Arthur Heymans
2018-06-05	nb/intel/pineview: Switch to POSTCAR_STAGE	Arthur Heymans
2018-06-05	nb/intel/i945: Switch to POSTCAR_STAGE	Arthur Heymans
2018-06-05	cpu/intel/car/core2: Improve a few things	Arthur Heymans
2018-06-05	cpu/intel/car/core2: Prepare for POSTCAR_STAGE support	Arthur Heymans
2018-06-04	security/tpm: Unify the coreboot TPM software stack	Philipp Deppenwiese