coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2012-07-24	Remove code that enables/disables VMX in coreboot on chromebooks.	Ronald G. Minnich
2012-07-04	Intel cpus: Extend cache to cover complete Flash Device	Kyösti Mälkki
2012-07-04	Intel model_106cx: change CAR to model_6ex	Kyösti Mälkki
2012-07-04	Intel cpus: delete dead CAR code and whitespace fixes	Kyösti Mälkki
2012-07-04	Intel cpus: use CPU_ADDR_BITS from Kconfig during CAR	Kyösti Mälkki
2012-07-02	remove CONFIG_SERIAL_CPU_INIT	Sven Schnelle
2012-07-02	Use broadcast SIPI to startup siblings	Sven Schnelle
2012-07-02	Intel CPUs: execute microcode update only once per core	Kyösti Mälkki
2012-06-19	Enable Intel PECI on Model 6fx CPUs	Sven Schnelle
2012-05-29	Drop config variable CPU_MODEL_INDEX	Stefan Reinauer
2012-05-08	Clean up #ifs	Patrick Georgi
2012-05-03	Fix register corruption during Intel Microcode update	Stefan Reinauer
2012-05-02	Don't include console.h in microcode.c when compiling with ROMCC	Stefan Reinauer
2012-04-30	Fix up Sandybridge C state generation code	Stefan Reinauer
2012-04-30	Rework ACPI CST table generation	Stefan Reinauer
2012-04-26	microcode: print date of microcode and unify output	Stefan Reinauer
2012-04-26	Revamp Intel microcode update code	Stefan Reinauer
2012-04-25	Replace cache control magic numbers with symbols	Patrick Georgi
2012-04-06	Fix support for RAM-less multi-processor init	Kyösti Mälkki
2012-04-05	Add support for Intel Sandybridge CPU	Stefan Reinauer
2012-04-03	Add support for Intel Turbo Boost feature	Stefan Reinauer
2012-04-02	Apply cache-as-ram conditionally on socket mPGA604	Kyösti Mälkki
2012-03-31	Whitespace fixes	Patrick Georgi
2012-03-31	Intel cpus: get MAXPHYADDR at runtime for new CAR	Kyösti Mälkki
2012-03-31	Intel cpus: add hyper-threading CPU support to new CAR	Kyösti Mälkki
2012-03-31	Intel cpus: improve CPU compatibility of new CAR	Kyösti Mälkki
2012-03-31	Intel cpus: apply some good programming practices in new CAR	Kyösti Mälkki
2012-03-31	Intel cpus: cache actual size of the Flash ROM device	Kyösti Mälkki
2012-03-31	Intel cpus: copy model_6ex CAR code	Kyösti Mälkki
2012-03-25	Intel cpus: Fix deadlock on hyper-threading init	Kyösti Mälkki
2012-03-17	Intel cpus: Include CAR from socket	Kyösti Mälkki
2012-02-16	Intel cpus: use CPU_PHYSMASK_HI define in CAR	Kyösti Mälkki
2012-02-15	Intel model_106cx: Use symbolic names for MTRR bits	Kyösti Mälkki
2012-02-10	Intel cpus: apply un-written naming rules	Kyösti Mälkki
2012-02-09	Add Intel Socket LGA771	Sven Schnelle
2012-01-10	MTRR: get physical address size from CPUID	Sven Schnelle
2012-01-09	ACPI: mark empty get_cst_entries() weak	Sven Schnelle
2011-11-01	Remove XIP_ROM_BASE	Patrick Georgi
2011-10-30	Fix slow CAR execution introduced by 7c7d87182feb78cb2bc02fb3558bef56a41682c9	Rudolf Marek
2011-10-28	Get rid of the old romstage-as-bootblock ROM layout	Patrick Georgi
2011-10-28	Get rid of AUTO_XIP_ROM_BASE	Patrick Georgi
2011-10-25	SPEEDSTEP: write _CST tables	Sven Schnelle
2011-10-18	Activate older Xeon P4 microcodes	Kyösti Mälkki
2011-09-09	Crank up CPU speed on Intel Core and Core2 CPUs	Patrick Georgi
2011-08-04	cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.	Keith Hui
2011-05-03	Enable caching for ROM area in model_6ex/cache_as_ram.inc	Sven Schnelle
2011-04-21	more ifdef -> if fixes	Stefan Reinauer
2011-04-14	Use symbolic names for some MTRR bits instead of numbers in CAR code	Stefan Reinauer
2011-04-11	Unify use of post_code	Alexandru Gagniuc
2011-01-27	oops. this is weird. CAR addresses should be specified in the socket and not in	Stefan Reinauer