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path: root/src/cpu/intel
AgeCommit message (Expand)Author
2016-03-10northbridge/intel/i440bx: Unify UDELAY selectionStefan Reinauer
2016-03-08x86 chipsets: utilize x86_setup_mtrrs_with_detect()Aaron Durbin
2016-02-26tree wide: Convert "if (CONFIG_.*_TPM.*)" to "if (IS_ENABLED(...))"Denis 'GNUtoo' Carikli
2016-02-14CPU/intel: Add missing license headersDamien Roth
2016-02-12Make MRC vs native a config rather than making a separate chipset for it.Vladimir Serbinenko
2016-02-10cpu/intel/microcode: allow microcode to be loaded in romstageAaron Durbin
2015-12-06Remove #ifdef checks on Kconfig symbolsMartin Roth
2015-12-06fsp_model_406dx: use external microcode .h files for rangeleyMartin Roth
2015-12-02x86/smm: Initialize SMM on some CPUs one-by-oneDamien Zammit
2015-11-24cpu/intel/socket_FCBGA559: Add new socket for Atom D5xxDamien Zammit
2015-11-20fsp1_0: Remove hardcoded microcode locationsMartin Roth
2015-11-16intel/fsp_model_406dx: Load APs microcode in model_406dx_initDavid Guckian
2015-11-16intel/fsp_rangeley: Load BSP microcode in bootblockDavid Guckian
2015-11-10cpu/intel: Add socket BGA1284Marc Jones
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-10-31sandybridge: Disable parallel CPU initializationNico Huber
2015-10-28cpu/intel/fsp_model_206ax: Load microcode in corebootMartin Roth
2015-10-23cpu/intel: Move Power notification ASL code into `common/acpi`Paul Menzel
2015-10-22Revert "Remove sandybridge and ivybridge FSP code path"Martin Roth
2015-10-15cpu/mtrr.h: Fix macro names for MTRR registersAlexandru Gagniuc
2015-10-14Revert "Remove FSP Rangeley SOC and mohonpeak board support"Martin Roth
2015-10-08arch/x86/bootblock: Do not include non-code files in bootblock.SAlexandru Gagniuc
2015-10-07x86/bootblock: Use LDFLAGS_bootblock to enable garbage collectionAlexandru Gagniuc
2015-10-03Remove FSP Rangeley SOC and mohonpeak board supportAlexandru Gagniuc
2015-10-03Remove sandybridge and ivybridge FSP code pathAlexandru Gagniuc
2015-10-03sandybridge ivybridge: Treat native init as first class citizenAlexandru Gagniuc
2015-09-30cpu: microcode: Use microcode stored in binary formatAlexandru Gagniuc
2015-09-24coreboot: move TS_END_ROMSTAGE to one spotAaron Durbin
2015-09-09intel/model_2065x/Kconfig: Don't use LAPIC_MONOTONIC_TIMERMartin Roth
2015-09-04x86: remove cpu_incs as romstage Make variableAaron Durbin
2015-08-25Intel: Remove CACHE_MRC_BIN - 'selected' everywhere in KconfigMartin Roth
2015-07-29Add SoC specific microcode update check in ramstageRizwan Qureshi
2015-07-07x86: Drop -Wa,--divideStefan Reinauer
2015-06-10model_2065x: Use common i945-ivy TSEG SMM init.Vladimir Serbinenko
2015-06-10model_206ax: Fix APIC map when HT is disabled.Vladimir Serbinenko
2015-06-10fsp_model_206ax: Use common i945-ivy tseg SMM init.Vladimir Serbinenko
2015-06-09stage_cache: use cbmem init hooksAaron Durbin
2015-06-09Create i945-ivy smm tseg init based on ivy code.Vladimir Serbinenko
2015-06-08Remove empty lines at end of fileElyes HAOUAS
2015-06-05device_ops: add device_t argument to acpi_fill_ssdt_generatorAlexander Couzens
2015-06-04Remove address from GPLv2 headersPatrick Georgi
2015-06-02cbfs: new API and better program loadingAaron Durbin
2015-05-28smm: Merge configs SMM_MODULES and SMM_TSEGVladimir Serbinenko
2015-05-28Migrate fsp_206ax to SMM_MODULESVladimir Serbinenko
2015-05-28Migrate 2065x to SMM_MODULESVladimir Serbinenko
2015-05-28Migrate 206ax to SMM_MODULESVladimir Serbinenko
2015-05-28intel: Remove pstate_coord_type.Vladimir Serbinenko
2015-05-27Move TPM code out of chromeosVladimir Serbinenko
2015-05-26acpigen: Remove all explicit length trackingVladimir Serbinenko
2015-05-26speedstep: Don't supply weak get_cst_entries.Vladimir Serbinenko
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