coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2014-07-30	cpu/intel: Add fsp version of model 406dx (Rangeley / Atom C2000)	Martin Roth
2014-07-30	cpu/intel/model_2065x/model_2065x_init.c: Remove dead code	Edward O'Callaghan
2014-07-29	sandy/ivybridge: Native raminit.	Vladimir Serbinenko
2014-07-23	cpu/intel/fsp_model_206ax/model_206ax_init.c: Use macro `IS_ENABLED()`	Paul Menzel
2014-07-19	intel/model_2065x: Remove dead code.	Vladimir Serbinenko
2014-07-17	cpu,Makefile.inc: Trivial - drop trailing blank lines at EOF	Edward O'Callaghan
2014-07-10	intel/haswell: add vmx support w/Kconfig option	Matt DeVillier
2014-07-08	cpu: Trivial - drop trailing blank lines at EOF	Edward O'Callaghan
2014-07-05	Drop redundant select CACHE_AS_RAM	Kyösti Mälkki
2014-07-05	intel: Make monotonic timer a first class citizen	Edward O'Callaghan
2014-06-17	intel/model_2065x: Add 20652 microcode.	Vladimir Serbinenko
2014-05-30	cpu/intel/fsp_model_206ax: change realpath to readlink	Martin Roth
2014-05-17	build: separate CPPFLAGS from CFLAGS	Patrick Georgi
2014-05-17	build: CPPFLAGS is more common than INCLUDES	Patrick Georgi
2014-05-13	cpu/intel: Add CPU socket rPGA988B	Zaolin
2014-05-10	Replace SERIAL_CPU_INIT with PARALLEL_CPU_INIT	Kyösti Mälkki
2014-05-09	cougar_canyon2: Switch CPU/NB/SB to the shared FSP code	Martin Roth
2014-05-06	Introduce stage-specific architecture for coreboot	Furquan Shaikh
2014-05-05	haswell: move to mp_init library	Aaron Durbin
2014-05-03	Move ARCH_* from board/Kconfig to cpu or soc Kconfig.	Furquan Shaikh
2014-04-26	Rename coreboot_ram stage to ramstage	Furquan Shaikh
2014-04-26	Get rid of HAVE_INIT_TIMER config option	Furquan Shaikh
2014-03-20	rmodules: use rmodtool to create rmodules	Aaron Durbin
2014-03-16	Make POST device configurable.	Idwer Vollering
2014-02-25	Remove CACHE_ROM.	Vladimir Serbinenko
2014-02-20	intel/model_2065x: Fix APICID generation.	Vladimir Serbinenko
2014-02-16	haswell: backup the default SMM region on resume	Aaron Durbin
2014-02-15	coreboot: infrastructure for different ramstage loaders	Aaron Durbin
2014-02-12	PCI: Drop includes under cpu	Kyösti Mälkki
2014-02-06	usbdebug: Drop obsolete code	Kyösti Mälkki
2014-02-01	cpu/intel/model_2065x: Add model 20652	Vladimir Serbinenko
2014-01-30	cpu/intel: allow non-packaged scoped turbo setting	Aaron Durbin
2014-01-30	coreboot: config to cache ramstage outside CBMEM	Aaron Durbin
2014-01-30	vboot: provide empty vboot_verify_firmware()	Aaron Durbin
2014-01-28	intel: fix microcode compilation failure in bootblock	Aaron Durbin
2014-01-26	src/cpu: Fix spelling of MTTR to MTRR	Paul Menzel
2014-01-23	intel/microcode: Remove leftover MICROCODE_INCLUDE_PATH.	Vladimir Serbinenko
2014-01-16	cpu/intel: Remove dummy terminators from microcode blobs	Alexandru Gagniuc
2014-01-16	cpu/intel: Make all Intel CPUs load microcode from CBFS	Alexandru Gagniuc
2014-01-15	nehalem/sandy/ivy/haswell: Enable WRPROT cache for all of flash	Kyösti Mälkki
2014-01-15	Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR	Kyösti Mälkki
2014-01-11	intel/fsp: Fix microcode including	Patrick Georgi
2013-12-21	haswell: Update microcode revision	Duncan Laurie
2013-12-17	cpu/intel: Do not rely on CBFS microcode having a terminator	Alexandru Gagniuc
2013-12-13	cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS	Alexandru Gagniuc
2013-12-12	haswell: Export functions for CPU family+model and stepping	Duncan Laurie
2013-12-12	haswell: Update ULT microcode to rev 14h	Duncan Laurie
2013-12-07	haswell: VR controller configuration	Aaron Durbin
2013-12-07	haswell: Misc power management setup and fixes	Duncan Laurie
2013-12-05	cpu: Remove BOARD_MICROCODE_CBFS_GENERATE Kconfig option	Alexandru Gagniuc