coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2013-03-18	haswell: move call site of save_mrc_data()	Aaron Durbin
2013-03-18	haswell: romstage: pass stack pointer and MTRRs	Aaron Durbin
2013-03-18	haswell: unify romstage logic	Aaron Durbin
2013-03-18	haswell: adjust CAR usage	Aaron Durbin
2013-03-18	haswell: enable caching before SMM initialization	Aaron Durbin
2013-03-18	haswell: Clear correct number of MCA banks	Aaron Durbin
2013-03-18	haswell: move definition of CORE_THREAD_COUNT_MSR	Aaron Durbin
2013-03-18	haswell: Use SMM Modules	Aaron Durbin
2013-03-17	x86 intel: Add Firmware Interface Table support	Aaron Durbin
2013-03-14	haswell: Add ULT CPUID and updated microcode	Duncan Laurie
2013-03-14	haswell: Properly Guard Engergy Policy by CPUID	Aaron Durbin
2013-03-14	haswell: Add initial support for Haswell platforms	Aaron Durbin
2013-03-07	Fix socket LGA775	Kyösti Mälkki
2013-03-01	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel
2013-02-14	sconfig: rename lapic_cluster -> cpu_cluster	Stefan Reinauer
2013-02-11	Intel: Replace MSR 0xcd with MSR_FSB_FREQ	Patrick Georgi
2013-02-09	speedstep: Deduplicate some MSR identifiers	Patrick Georgi
2013-02-09	document Intel VMX locking behavior	Mike Frysinger
2013-01-30	Extend CBFS to support arbitrary ROM source media.	Hung-Te Lin
2012-11-27	Get rid of drivers class	Patrick Georgi
2012-11-13	Add spinlock to serialize Intel microcode updates	Stefan Reinauer
2012-11-13	Fix CONFIG_MAX_CPU set to 1 CPU build problem	Stefan Reinauer
2012-11-12	ivybridge: Catch unknown CPU revisions	Stefan Reinauer
2012-11-12	Initialize the VMX MSR	Marc Jones
2012-11-12	Revert "Remove code that enables/disables VMX in coreboot on chromebooks."	Marc Jones
2012-11-12	sandybridge: Correct reporting of cores and threads	Stefan Reinauer
2012-11-07	Leave power control registers unlocked	Sameer Nanda
2012-11-06	cpu/intel/model_1067x: Add proper c-state/p-state/thermal support	Nico Huber
2012-11-06	intel/socket_BGA956: enable speedstep, CAR, MMX, SSE	Patrick Georgi
2012-11-05	Overhaul speedstep code	Nico Huber
2012-11-05	Fix some indentation flaws and break very long lines	Nico Huber
2012-11-02	Correct FSB reading in speedstep ACPI	Nico Huber
2012-11-01	Merge cpu/intel/acpi.h into cpu/intel/speedstep.h	Nico Huber
2012-10-30	Add support for socket LGA775	Stefan Tauner
2012-10-07	Fix typo in mPGA603 socket	Kyösti Mälkki
2012-10-07	Remove chip.h files without config structure	Kyösti Mälkki
2012-09-05	buildsystem: Make CPU microcode updating more configurable	Alexandru Gagniuc
2012-08-27	Intel model_106cx: change CAR to HT-capable	Kyösti Mälkki
2012-08-22	Auto-declare chip_operations	Kyösti Mälkki
2012-08-09	Synchronize rdtsc instructions	Stefan Reinauer
2012-08-03	Intel CPUs: Fix counting of CPU cores	Kyösti Mälkki
2012-07-31	Revert "Use broadcast SIPI to startup siblings"	Sven Schnelle
2012-07-31	Revert "remove CONFIG_SERIAL_CPU_INIT"	Sven Schnelle
2012-07-26	CPU: Add option to set TCC activation offset	Duncan Laurie
2012-07-26	ACPI: Add a method to notify OS to re-read _PPC	Duncan Laurie
2012-07-26	ACPI: Add function to write _PPC using NVS	Duncan Laurie
2012-07-26	Drop CONFIG_CPU_MODEL_NAME and fix CPU name displayed in logs	Stefan Reinauer
2012-07-26	Enable Microcode in CBFS for all SandyBridge/IvyBridge systems	Stefan Reinauer
2012-07-25	Fix comment to reference IvyBridge, too	Stefan Reinauer
2012-07-25	Include SandyBridge Microcode when IvyBridge is enabled	Stefan Reinauer