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path: root/src/cpu/intel
AgeCommit message (Expand)Author
2014-08-30sandybridge: Add native sandybridgeVladimir Serbinenko
2014-08-18cpu/intel/fsp_model_406dx: code cleanupMartin Roth
2014-08-12cpu/intel/XXX/acpi.c: Fix coding style violationMartin Roth
2014-08-10model_106cx: don't blindly set Kconfig settingsAaron Durbin
2014-08-10cpu/intel/model_1067x: avoid null-pointer dereferencePatrick Georgi
2014-08-04cpu/intel: Fix out-of-bounds read due to off-by-one in conditionEdward O'Callaghan
2014-07-30model_206ax_init.c: Trivial - fix indentEdward O'Callaghan
2014-07-30cpu/intel: Add fsp version of model 406dx (Rangeley / Atom C2000)Martin Roth
2014-07-30cpu/intel/model_2065x/model_2065x_init.c: Remove dead codeEdward O'Callaghan
2014-07-29sandy/ivybridge: Native raminit.Vladimir Serbinenko
2014-07-23cpu/intel/fsp_model_206ax/model_206ax_init.c: Use macro `IS_ENABLED()`Paul Menzel
2014-07-19intel/model_2065x: Remove dead code.Vladimir Serbinenko
2014-07-17cpu,Makefile.inc: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
2014-07-10intel/haswell: add vmx support w/Kconfig optionMatt DeVillier
2014-07-08cpu: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
2014-07-05Drop redundant select CACHE_AS_RAMKyösti Mälkki
2014-07-05intel: Make monotonic timer a first class citizenEdward O'Callaghan
2014-06-17intel/model_2065x: Add 20652 microcode.Vladimir Serbinenko
2014-05-30cpu/intel/fsp_model_206ax: change realpath to readlinkMartin Roth
2014-05-17build: separate CPPFLAGS from CFLAGSPatrick Georgi
2014-05-17build: CPPFLAGS is more common than INCLUDESPatrick Georgi
2014-05-13cpu/intel: Add CPU socket rPGA988BZaolin
2014-05-10Replace SERIAL_CPU_INIT with PARALLEL_CPU_INITKyösti Mälkki
2014-05-09cougar_canyon2: Switch CPU/NB/SB to the shared FSP codeMartin Roth
2014-05-06Introduce stage-specific architecture for corebootFurquan Shaikh
2014-05-05haswell: move to mp_init libraryAaron Durbin
2014-05-03Move ARCH_* from board/Kconfig to cpu or soc Kconfig.Furquan Shaikh
2014-04-26Rename coreboot_ram stage to ramstageFurquan Shaikh
2014-04-26Get rid of HAVE_INIT_TIMER config optionFurquan Shaikh
2014-03-20rmodules: use rmodtool to create rmodulesAaron Durbin
2014-03-16Make POST device configurable.Idwer Vollering
2014-02-25Remove CACHE_ROM.Vladimir Serbinenko
2014-02-20intel/model_2065x: Fix APICID generation.Vladimir Serbinenko
2014-02-16haswell: backup the default SMM region on resumeAaron Durbin
2014-02-15coreboot: infrastructure for different ramstage loadersAaron Durbin
2014-02-12PCI: Drop includes under cpuKyösti Mälkki
2014-02-06usbdebug: Drop obsolete codeKyösti Mälkki
2014-02-01cpu/intel/model_2065x: Add model 20652Vladimir Serbinenko
2014-01-30cpu/intel: allow non-packaged scoped turbo settingAaron Durbin
2014-01-30coreboot: config to cache ramstage outside CBMEMAaron Durbin
2014-01-30vboot: provide empty vboot_verify_firmware()Aaron Durbin
2014-01-28intel: fix microcode compilation failure in bootblockAaron Durbin
2014-01-26src/cpu: Fix spelling of MTTR to MTRRPaul Menzel
2014-01-23intel/microcode: Remove leftover MICROCODE_INCLUDE_PATH.Vladimir Serbinenko
2014-01-16cpu/intel: Remove dummy terminators from microcode blobsAlexandru Gagniuc
2014-01-16cpu/intel: Make all Intel CPUs load microcode from CBFSAlexandru Gagniuc
2014-01-15nehalem/sandy/ivy/haswell: Enable WRPROT cache for all of flashKyösti Mälkki
2014-01-15Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRRKyösti Mälkki
2014-01-11intel/fsp: Fix microcode includingPatrick Georgi
2013-12-21haswell: Update microcode revisionDuncan Laurie
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