summaryrefslogtreecommitdiff
path: root/src/cpu/intel
AgeCommit message (Expand)Author
2020-07-14cpu/intel/model_1067x: Drop <cpu/x86/mp.h> includeElyes HAOUAS
2020-07-14src: Remove unused 'include <cpu/x86/msr.h>'Elyes HAOUAS
2020-07-14src: Remove unused 'include <types.h>'Elyes HAOUAS
2020-07-10cpu/intel/haswell/finalize.c: Drop dead codeAngel Pons
2020-07-09cpu/intel/model_2065x/model_2065x_init.c: Drop dead codeAngel Pons
2020-07-09cpu/intel/model_206ax/finalize.c: Drop dead codeAngel Pons
2020-07-08haswell: relocate `romstage_common` to northbridgeAngel Pons
2020-07-08nb/intel/haswell: Drop unnecessary variableAngel Pons
2020-07-08haswell: drop unused function parameterAngel Pons
2020-06-22cpu/x86/lapic: Support x86_64 and clean up codePatrick Rudolph
2020-06-16sb,soc/intel: Replace smm_southbridge_enable_smi()Kyösti Mälkki
2020-06-15gm45 boards: Factor out MAX_CPUSAngel Pons
2020-06-15pineview boards: Factor out MAX_CPUSAngel Pons
2020-06-15haswell boards: Factor out MAX_CPUSAngel Pons
2020-06-15arrandale boards: Factor out MAX_CPUSAngel Pons
2020-06-15sandybridge boards: Factor out MAX_CPUSAngel Pons
2020-06-15cpu/intel: Remove obsolete comment in CAR setupKyösti Mälkki
2020-06-15arch/x86: Remove NO_FIXED_XIP_ROM_SIZEKyösti Mälkki
2020-06-13cpu/intel/car: Use symbols for CAR MTRR setupKyösti Mälkki
2020-06-06src: Remove unused 'include <cpu/x86/mtrr.h>'Elyes HAOUAS
2020-06-06cpu/intel/haswell: Remove unused 'include <cpu/x86/bist.h>'Elyes HAOUAS
2020-06-06src: Remove unused '#include <cpu/x86/smm.h>'Elyes HAOUAS
2020-06-04cpu/intel/slot_1: Select 16KiB bootblock if console is enabledKeith Hui
2020-06-02src: Remove unused '#include <cpu/x86/lapic.h>'Elyes HAOUAS
2020-05-28arch/x86: Remove more romcc leftoversKyösti Mälkki
2020-05-28cpu/intel/common: Fix typo in commentElyes HAOUAS
2020-05-18src: Remove leading blank lines from SPDX headerElyes HAOUAS
2020-05-13src: Remove unused '#include <stdint.h>'Elyes HAOUAS
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
2020-05-10src/cpu: Replace GPLv2 long form headers with SPDX headerElyes HAOUAS
2020-05-09src/: Replace GPL boilerplate with SPDX headersPatrick Georgi
2020-05-06treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi
2020-05-06treewide: Move "is part of the coreboot project" line in its own commentPatrick Georgi
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
2020-05-01src: Remove unused 'include <cpu/x86/cache.h>'Elyes HAOUAS
2020-04-28device: Constify struct device * parameter to acpi_fill_ssdt()Furquan Shaikh
2020-04-04src/cpu: Use SPDX for GPL-2.0-only filesAngel Pons
2020-03-23acpi: Change Processor ACPI Name (Intel only)Christian Walter
2020-03-15cpu/intel/model_2065x: Add missing CPU IDsAngel Pons
2020-03-15treewide: Replace uses of "Nehalem"Angel Pons
2020-03-15nb/intel/nehalem: Rename to ironlakeAngel Pons
2020-03-04cpu/intel/model_206ax: Lock MSR on all coresPatrick Rudolph
2020-03-03cpu/intel/slot_1: Cache romstage XIP executionArthur Heymans
2020-02-24src: capitalize 'RAM'Elyes HAOUAS
2020-02-09cpu/intel: Drop unused fileElyes HAOUAS
2020-01-18cpu/intel/model_6?x{slot_1}: Leave enabling CONFIG_SMP to the mainboardKeith Hui
2020-01-09drivers/pc80/rtc: Separate {get|set}_option() prototypesKyösti Mälkki
2019-12-27cpu/intel/microcode: Apply more strict guard for assembly filesKyösti Mälkki
2019-12-26src/x86|cpu/intel: Hardcode FIT and IDMarshall Dawson
2019-12-19arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHEKyösti Mälkki
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 20:05:53 +0000