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coreboot
2560p
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autoport-hsw
broadwell_refcode
e6230
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haswell-mrc
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Some coreboot project code with my work
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cpu
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x86
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16bit
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entry16.inc
Age
Commit message (
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Author
2018-02-15
cpu/x86/16bit/entry16.inc: Fix typo in comment
Paul Menzel
2016-08-23
src/cpu: Capitalize CPU, APIC and IOAPIC typo fix
Elyes HAOUAS
2016-07-31
src/cpu: Capitalize CPU
Elyes HAOUAS
2016-07-31
src/cpu: Capitalize ROM and RAM
Elyes HAOUAS
2016-03-03
cpu/x86/16bit: rename _start -> _start16bit
Aaron Durbin
2015-11-19
x86: Add Kconfig to disable early bootblock postcodes
Martin Roth
2015-06-08
Remove empty lines at end of file
Elyes HAOUAS
2014-02-19
x86 bootblock: improve clang compatibility
Patrick Georgi
2012-03-16
Fix address of IDT in real-mode entry
Kyösti Mälkki
2012-01-21
trivial: spelling fixes in comments
Vikram Narayanan
2011-11-24
Remove unused code files and cosmetic changes
Kyösti Mälkki
2011-11-22
Fix post_code in 16bit entry
Kyösti Mälkki
2011-10-13
Load an IDT with NULL limit
Stefan Reinauer
2010-04-27
Since some people disapprove of white space cleanups mixed in regular commits
Stefan Reinauer
2004-11-04
tell people that the segment descriptors are different for ROMCC and
Li-Ta Lo
2004-10-14
- Add new cvs code to cvs
Eric Biederman