| Age | Commit message (Expand) | Author |
|---|---|---|
| 2013-02-11 | Intel: Replace MSR 0xcd with MSR_FSB_FREQ | Patrick Georgi |
| 2012-11-27 | Remove AMD special case for LAPIC based udelay() | Patrick Georgi |
| 2012-07-25 | Fix LAPIC timer on Ivy Bridge systems | Stefan Reinauer |
| 2012-07-23 | Re-initialize Local APIC timer on APs | Stefan Reinauer |
| 2012-06-12 | udelay: add missing bus frequency | Sven Schnelle |
| 2012-04-05 | Fix timer frequency detection on Sandybridge | Stefan Reinauer |
| 2011-05-10 | This replaces the fixed shift values in the apic timer init with macros. | Vikram Narayanan |
| 2009-07-21 | * rework tsc based timer code to use inb instead of outb for calibration | Stefan Reinauer |
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index : coreboot | |
| Some coreboot project code with my work | vimacs |
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