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2016-08-18Kconfig: rename BOOT_MEDIA_SPI_BUS to BOOT_DEVICE_SPI_FLASH_BUSAaron Durbin
Provide a default value of 0 in drivers/spi as there weren't default values aside from specific mainboards and arch/x86. Remove any default 0 values while noting to keep the option's default to 0. BUG=chrome-os-partner:56151 Change-Id: If9ef585e011a46b5cd152a03e41d545b36355a61 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16192 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31src/cpu: Capitalize CPUElyes HAOUAS
Change-Id: I58d5c16de796a91fa14d8db78722024266c09a94 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15934 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31src/cpu: Capitalize ROM and RAMElyes HAOUAS
Change-Id: I103167a0c39627bcd2ca1d0d4288eb5df02a6cd2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15935 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-27cpu/x86: Support CPUs without rdmsr/wrmsr instructionsLee Leahy
Quark does not support the rdmsr and wrmsr instructions. In this case use a SOC specific routine to support the setting of the MTRRs. Migrate the code from FSP 1.1 to be x86 CPU common. Since all rdmsr/wrmsr accesses are being converted, fix the build failure for quark in lib/reg_script.c. Move the soc_msr_x routines and their depencies from romstage/mtrr.c to reg_access.c. TEST=Build and run on Galileo Gen2 Change-Id: Ibc68e696d8066fbe2322f446d8c983d3f86052ea Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15839 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-22cpu/x86/mtrr: correct variable MTRR calculation around 1MiB boundaryAaron Durbin
The fixed MTRRs cover the range [0:1MiB). While calculating the variable MTRR usage the 1MiB boundary is checked such that an excessive number of MTRRs aren't used because of unnatural alignment at the low end of the physical address space. Howevever, those checks weren't inclusive of the 1MiB boundary. As such a variable MTRR could be used for a range which is actually covered by the fixed MTRRs when the end address is equal to 1MiB. Likewise, if the starting address of the range lands on the 1MiB boundary then more variable MTRRs are calculated in order to meet natural alignment requirements. Before: MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x0000000000100000 size 0x00060000 type 0 0x0000000000100000 - 0x000000007b800000 size 0x7b700000 type 6 0x000000007b800000 - 0x00000000b0000000 size 0x34800000 type 0 0x00000000b0000000 - 0x00000000c0000000 size 0x10000000 type 1 0x00000000c0000000 - 0x0000000100000000 size 0x40000000 type 0 0x0000000100000000 - 0x0000000180000000 size 0x80000000 type 6 CPU physical address size: 39 bits MTRR: default type WB/UC MTRR counts: 7/17. MTRR: WB selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000007ffff00000 type 0 MTRR: 1 base 0x000000007b800000 mask 0x0000007fff800000 type 0 MTRR: 2 base 0x000000007c000000 mask 0x0000007ffc000000 type 0 MTRR: 3 base 0x0000000080000000 mask 0x0000007fe0000000 type 0 MTRR: 4 base 0x00000000a0000000 mask 0x0000007ff0000000 type 0 MTRR: 5 base 0x00000000b0000000 mask 0x0000007ff0000000 type 1 MTRR: 6 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0 After: MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x0000000000100000 size 0x00060000 type 0 0x0000000000100000 - 0x000000007b800000 size 0x7b700000 type 6 0x000000007b800000 - 0x00000000b0000000 size 0x34800000 type 0 0x00000000b0000000 - 0x00000000c0000000 size 0x10000000 type 1 0x00000000c0000000 - 0x0000000100000000 size 0x40000000 type 0 0x0000000100000000 - 0x0000000180000000 size 0x80000000 type 6 CPU physical address size: 39 bits MTRR: default type WB/UC MTRR counts: 6/8. MTRR: WB selected as default type. MTRR: 0 base 0x000000007b800000 mask 0x0000007fff800000 type 0 MTRR: 1 base 0x000000007c000000 mask 0x0000007ffc000000 type 0 MTRR: 2 base 0x0000000080000000 mask 0x0000007fe0000000 type 0 MTRR: 3 base 0x00000000a0000000 mask 0x0000007ff0000000 type 0 MTRR: 4 base 0x00000000b0000000 mask 0x0000007ff0000000 type 1 MTRR: 5 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0 BUG=chrome-os-partner:55504 Change-Id: I7feab38dfe135f5e596c9e67520378a406aa6866 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15780 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-22ACPI S3: Move SMP trampoline recoveryKyösti Mälkki
No need to make low memory backup unless we are on S3 resume path. Hide those details from ACPI. Change-Id: Ic08b6d70c7895b094afdb3c77e020ff37ad632a1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15241 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-17intel/sch: Merge northbridge and southbridge in src/socStefan Reinauer
Change-Id: I6ea9b9d2353c0d767c837e6d629b45f23b306f6e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14599 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2016-05-06cpu/x86: don't treat all chipsets the same regarding XIP_ROM_SIZEAaron Durbin
Previously, the XIP_ROM_SIZE Kconfig variable is used globally on x86 platforms with the assumption that all chipsets utilize this value. For the chipsets which do not use the variable it can lead to unnecessary alignment constraints in cbfs for romstage. Therefore, allow those chipsets a path to not be burdened by not passing '-P $(XIP_ROM_SIZE)' to cbfstool when adding romstage. Change-Id: Id8692df5ecec116a72b8e5886d86648ca959c78b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14625 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-06cpu/x86/mp_init: reduce exposure of internal implementationAaron Durbin
With all users converted to using the mp_ops callbacks there's no need to expose that surface area. Therefore, keep it all within the mp_init compilation unit. Change-Id: Ia1cc5326c1fa5ffde86b90d805b8379f4e4f46cd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14598 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-04cpu/x86: combine multiprocessor and SMM initializationAaron Durbin
In order to reduce code duplication provide a common flow through callback functions that performs the multiprocessor and optionally SMM initialization. The existing MP flight records are utilized but a common flow is provided such that the chipset/cpu only needs to provide a mp_ops structure which has callbacks to gather info and provide hooks at certain points in the sequence. All current users of the MP code can be switched over to this flow since there haven't been any flight records that are overly complicated and long. After the conversion has taken place most of the surface area of the MP API can be hidden away within the compilation unit proper. Change-Id: I6f70969631012982126f0d0d76e5fac6880c24f0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14557 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-04cpu/x86: remove BACKUP_DEFAULT_SMM_REGION optionAaron Durbin
Unconditionally provide the backup default SMM area API. There's no reason to guard the symbols behind anything since linker garbage collection is implemented. A board or chipset is free to use the code or not without needing to select an option. Change-Id: I14cf1318136a17f48ba5ae119507918190e25387 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14561 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-04cpu/x86/smm_module_loader: always build with SMM module supportAaron Durbin
The SMM module loader code was guarded by CONFIG_SMM_TSEG, however that's not necessary. It's up to the chipset to take advantage of the SMM module loading. It'll get optimized out if the code isn't used anyway so just expose the declarations. Change-Id: I6ba1b91d0c84febd4f1a92737b3d7303ab61b343 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14560 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-02cpu/x86/mp_init: remove unused callback argumentsAaron Durbin
The BSP and AP callback declarations both had an optional argument that could be passed. In practice that functionality was never used so drop it. Change-Id: I47fa814a593b6c2ee164c88d255178d3fb71e8ce Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14556 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-04-28soc/intel/apollolake: Add cache for BIOS ROMAndrey Petrov
Enable caching of BIOS region with variable MTRR. This is most useful if enabled early such as in bootblock. Change-Id: I39f33ca43f06fce26d1d48e706c97f097e3c10f1 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14480 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-04-11cpu/x86/tsc: Compile TSC timer for postcar as wellAndrey Petrov
Change-Id: I8fd79d438756aae03649e320d4d640cee284d88a Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14298 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-11cpu/x86/tsc: remove conditional compilationAaron Durbin
The delay_tsc.c compilation unit used the C preprocessor to conditionally compile different code paths. Instead of guarding large blocks of code allow the compiler to optimize out unreachable code. Change-Id: I660c21d6f4099b0d7aefa84b14f1e68d6fd732c3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14302 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-04-11cpu/x86/tsc: compile same code for all stagesAaron Durbin
The delay_tsc.c code took different paths depending __PRE_RAM__ being defined or not. Also, timer_monotonic_get() was only compiled in a !__PRE_RAM__ environment. Clean up the code paths by employing CAR_GLOBAL for the global state which allows the same code to be used in all stages. Lastly, handle apollolake fallout now that init_timer() is not needed in placeholders.c. Change-Id: Ia769fa71e2c9d8b11201a3896d117097f2cb7c56 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14301 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-04-11cpu/x86/tsc: prepare for CAR_GLOBAL in delay_tsc.cAaron Durbin
The current code in delay_tsc.c uses globals and is heavily guarded by a lot of preprocessor macros. In order to remove __PRE_RAM__ constraints one needs to use CAR_GLOBAL for the global variables. Therefore, abstract away direct access to the globals such that CAR_GLOBAL can be easily employed. Change-Id: I3350d1a762120476926c8d9f5f5a7aba138daf5f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14300 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-04-11src/cpu/x86: remove TSC_CALIBRATE_WITH_IOAaron Durbin
It's not selected by any path so it's a dead option with associated dead code. Remove the config option as well as the code paths that were never used any longer. Change-Id: Ie536eee54e5c63bd90192f413c69e0dd2fea9171 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14299 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Myles Watson <mylesgw@gmail.com>
2016-03-23arch/x86: introduce postcar stage/phaseAaron Durbin
Certain chipsets don't have a memory-mapped boot media so their code execution for stages prior to DRAM initialization is backed by SRAM or cache-as-ram. The postcar stage/phase handles the cache-as-ram situation where in order to tear down cache-as-ram one needs to be executing out of a backing store that isn't transient. By current definition, cache-as-ram is volatile and tearing it down leads to its contents disappearing. Therefore provide a shim layer, postcar, that's loaded into memory and executed which does 2 things: 1. Tears down cache-as-ram with a chipset helper function. 2. Loads and runs ramstage. Because those 2 things are executed out of ram there's no issue of the code's backing store while executing the code that tears down cache-as-ram. The current implementation makes no assumption regarding cacheability of the DRAM itself. If the chipset code wishes to cache DRAM for loading of the postcar stage/phase then it's also up to the chipset to handle any coherency issues pertaining to cache-as-ram destruction. Change-Id: Ia58efdadd0b48f20cfe7de2f49ab462306c3a19b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14140 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-18mtrr: Define a function for obtaining free var mtrrFurquan Shaikh
Instead of hard-coding var mtrr numbers in code, use this function to identify the first available variable mtrr. If no such mtrr is available, the function will return -1. Change-Id: I2a1e02cdb45c0ab7e30609641977471eaa2431fd Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14115 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-16cpu/x86: compile earlymtrr.c code for romstage as wellAndrey Petrov
In order to make this work earlymtrr.c needed to be removed from intel/truxton/romstage.c. It's not a ROMCC board so there's no reason to be including .c files. Change-Id: If4f5494a53773454b97b90fb856f7e52cadb3f44 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14094 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-16cpu/x86/mtrr: remove early_mtrr_* functionsAaron Durbin
I see no user of any of this code. Remove it. Change-Id: I776cd3d9ac6578ecb0fe6d98f15611e4463afb7a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14098 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-16cpu/x86/mtrr: move cache_ramstage() to its only userAaron Durbin
The Intel i3100 northbridge code is the only user of cache_ramstage(). Therefore, place it next to the sole consumer. Change-Id: If15fb8d84f98dce7f4de9e089ec33035622d8f74 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14097 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-08cpu/x86/mtrr: add helper function to detect variable MTRRsAaron Durbin
The current MTRR API doesn't allow one to detect variable MTRRs along with handling fixed MTRRs in one function call. Therefore, add x86_setup_mtrrs_with_detect() to perform the same actions as x86_setup_mtrrs() but always do the dynamic detection. Change-Id: I443909691afa28ce11882e2beab12e836e5bcb3d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13935 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-03-08cpu/x86: Sort some Kconfig optionsStefan Reinauer
Change-Id: I25ea327ed151e18ccb5d13626d44925d2a253d08 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/10012 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-05arch/x86: document CAR symbols and expose them in symbols.hAndrey Petrov
Attempt to better document the symbol usage in car.ld for cache-as-ram usage. Additionally, add _car_region_[start|end] that completely covers the entire cache-as-ram region. The _car_data_[start|end] symbols were renamed to _car_relocatable_data_[start|end] in the hopes of making it clearer that objects within there move. Lastly, all these symbols were added to arch/symbols.h. Change-Id: I1f1af4983804dc8521d0427f43381bde6d23a060 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13804 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-04arch/x86: always use _start as entry symbol for all stagesAaron Durbin
Instead of keeping track of all the combinations of entry points depending on the stage and other options just use _start. That way, there's no need to update the arch/header.ld for complicated cases as _start is always the entry point for a stage. Change-Id: I7795a5ee1caba92ab533bdb8c3ad80294901a48b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13882 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-04arch/x86: rename reset_vector -> _startAaron Durbin
In order to align the entry points for the various stages on x86 to _start one needs to rename the reset_vector symbol. The section is the same; it's just a symbol change. Change-Id: I0e6bbf1da04a6e248781a9c222a146725c34268a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13881 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-03cpu/x86/16bit: rename _start -> _start16bitAaron Durbin
In order to avoid collisions with other _start symbols while grepping and future ones be explicit about which _start this one is: the 16-bit one only used by the reset vector in the bootblock. Change-Id: I6d7580596c0e6602a87fb158633ce9d45910cec2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13880 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2016-03-03cpu/x86/16bit/reset16: mark reset vector executableAaron Durbin
It's helpful to see the reset vector in objdump output. Without it being marked executable it doesn't get displayed. Change-Id: I85cb72ea0727d3f3c2186ae20b9c5cfe5d23aeed Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13879 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2016-03-03cpu/x86/16bit/reset16: remove stale 32-bit jumpAaron Durbin
Patrick at least indicated this jump after the reset vector jump was a remnant from some construct used long ago in the project. It's not longer used (nor could I find where it was). Therefore, remove it. Change-Id: I31512c66a9144267739b08d5f9659c4fcde1b794 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13878 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2016-02-11cpu/x86/tsc: Compile delay_tsc.c for the bootblock as wellAlexandru Gagniuc
This is needed in a follow-on patch to enable udelay() handling on apollolake, which is a dependency for the console code. Change-Id: I7da6a060a91b83f3b32c5c5d269c102ce7ae3b8a Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/13302 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-02src: Fix various spelling and whitespace issues.Martin Roth
This fixes some spelling and whitespace issues that I came across while working on various things in the tree. There are no functional changes. Change-Id: I33bc77282f2f94a1fc5f1bc713e44f72db20c1ab Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13016 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-28Move object files to $(obj)/<class>/Nico Huber
Instead of tagging object files with .<class>, move them to a <class> directory below $(obj)/. This way we can keep a 1:1 mapping between source- and object-file names. The 1:1 mapping is a prerequisite for Ada, where the compiler refuses any other object-file name. Tested by verifying that the resulting coreboot.rom files didn't change for all of Jenkins' abuild configurations. Change-Id: Idb7a8abec4ea0a37021d9fc24cc8583c4d3bf67c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/13181 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-01-28Makefile: Make full use of src-to-obj macroNico Huber
There were several spots in the tree where the path to a per class object file was hardcoded. To make use of the src-to-obj macro for this, it had to be moved before the inclusion of subdirs. Which is fine, as it doesn't have dependencies beside $(obj). Tested by verifying that the resulting coreboot.rom files didn't change for all of Jenkins' abuild configurations. Change-Id: I2eb1beeb8ae55872edfd95f750d7d5a1cee474c4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/13180 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-21*/Makefile.inc: Compile files needed by uart8250 in x86 bootblockAlexandru Gagniuc
These files provide symbols needed by console and uart drivers. This was not an issue in the past, as we were not setting up a C environment this early in the boot process. Change-Id: Ied5106ac30a68971c8330e8f8270ab060994a89d Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/12869 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-20cpu: Fix typo that spelled "allocate" as "allocte."Jacob Laska
The error informing the user that the CPU device cannot be allocated has a typo incorrectly spelling "allocate" as "allocte". TEST=Compiled Change-Id: I2a6bad56133e375e2fd6a670593791414bf0dc2c Signed-off-by: Jacob Laska <jlaska91@gmail.com> Reviewed-on: https://review.coreboot.org/13030 Tested-by: build bot (Jenkins) Reviewed-by: Ben Frisch <bfrisch@xes-inc.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-12-02x86/smm: Initialize SMM on some CPUs one-by-oneDamien Zammit
We currently race in SMM init on Atom 230 (and potentially other CPUs). At least on the 230, this leads to a hang on RSM, likely because both hyperthreads mess around with SMBASE and other SMM state variables in parallel without coordination. The same behaviour occurs with Atom D5xx. Change it so first APs are spun up and sent to sleep, then BSP initializes SMM, then every CPU, one after another. Only do this when SERIALIZE_SMM_INITIALIZATION is set. Set the flag for Atom CPUs. Change-Id: I1ae864e37546298ea222e81349c27cf774ed251f Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/6311 Tested-by: build bot (Jenkins) Tested-by: BSI firmware lab <coreboot-labor@bsi.bund.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-24FSP 1.0: Fix CAR issues - broken timestamps and consoleBen Gardner
FSP 1.0 has a fixed-size temporary cache size and address and the entire cache is migrated in the FSP FspInitEntry() function. Previous code expected the symbol _car_data_start to be the same as CONFIG_DCACHE_RAM_BASE and _car_data_end to be the same as _preram_cbmem_console. FSP 1.0 is the only one that migrates _preram_cbmem_console. Others leave that where it is and extract the early console data in cbmemc_reinit(). Special handling is needed to handle that. Commit dd6fa93d broke both assumptions and so broke the timestamp table and console. The fix is to use CONFIG_DCACHE_RAM_BASE when calculating the offset and to use _preram_cbmem_console instead of _car_data_end for the console check. Change-Id: I6db109269b3537f7cb1300357c483ff2a745ffa7 Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: http://review.coreboot.org/12511 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-24Unify OBJCOPY arguments throughout various x86 stagesStefan Reinauer
Instead of having to have an ifeq() all across the code base, use $(target-objcopy). And correct target-objcopy to a value that objcopy actually understands. Change-Id: Id5dea6420bee02a044dc488b5086d109e806d605 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11090 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-19x86: Add Kconfig to disable early bootblock postcodesMartin Roth
The Intel cave creek chipset needs to have port 80 routing configured before any post codes can be sent to port 80h. Sending post codes out before the routing is done will hang the system. This patch allows us to disable the first couple of post codes that go out before the routing can be configured. The Kconfig symbol is selected by the cave creek chipset (fsp_i89xx). Change-Id: I9bf41669ec32744f87a1ed2de011d31c72ea38da Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12422 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: York Yang <york.yang@intel.com>
2015-11-14cpu/x86/lapic: Add stack overrun detectionTimothy Pearson
Change-Id: I03e43f38e0d2e51141208ebb169ad8deba77ab78 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11963 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30smm: 64bit fixesStefan Reinauer
Change-Id: I35dab4e66514948aafa912d993fb8d42c5a520a0 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11089 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-29smmhandler: on i945..nehalem, crash if LAPIC overlaps with ASEGPatrick Georgi
This mitigates the Memory Sinkhole issue (described on https://github.com/xoreaxeaxeax/sinkhole) by checking for the issue and crashing the system explicitly if LAPIC overlaps ASEG. This needs to happen without a data access (only code fetches) because data accesses could be tampered with. Don't try to recover because, if somebody tried to do shenanigans like these, we have to expect more. Sandybridge is safe because it does the same test in hardware, and crashes. Newer chipsets presumably do the same. This needs to be extended to deal with overlapping TSEG as well. Change-Id: I508c0b10ab88779da81d18a94b08dcfeca6f5a6f Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11519 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-10-15cpu/x86/mtrr: Add MTRR index and total MTRRs to error messagePaul Menzel
Change-Id: I626a11c17c9d05c174c507d50684e498c8604cbc Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11905 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-10-15cpu/mtrr.h: Fix macro names for MTRR registersAlexandru Gagniuc
We use UNDERSCORE_CASE. For the MTRR macros that refer to an MSR, we also remove the _MSR suffix, as they are, by definition, MSRs. Change-Id: Id4483a75d62cf1b478a9105ee98a8f55140ce0ef Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11761 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-10-14x86: add standalone verstage supportAaron Durbin
To support x86 verstage one needs a working buffer for vboot. That buffer resides in the cache-as-ram region which persists across verstage and romstage. The current assumption is that verstage brings cache-as-ram up and romstage tears cache-as-ram down. The timestamp, cbmem console, and the vboot work buffer are persistent through in both romstage and verstage. The vboot work buffer as well as the cbmem console are permanently destroyed once cache-as-ram is torn down. The timestamp region is migrated. When verstage is enabled the assumption is that _start is the romstage entry point. It's currently expected that the chipset provides the entry point to romstage when verstage is employed. Also, the car_var_*() APIs use direct access when in verstage since its expected verstage does not tear down cache-as-ram. Lastly, supporting files were added to verstage-y such that an x86 verstage will build and link. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados using separate verstage. Change-Id: I097aa0b92f3bb95275205a3fd8b21362c67b97aa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11822 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-07x86/bootblock: Use LDFLAGS_bootblock to enable garbage collectionAlexandru Gagniuc
The x86 bootblock linking is a mess. The bootblock is treated in a very special manner, and never received the update to link-time garbage collection. On newer x86 platforms, the boot media is no longer memory-mapped. That means we need to do a lot more setup in the bootblock. ROMCC is unsuitable for this task, and walkcbfs only works on memory-mapped CBFS. We need to revise the x86 bootflow for this new case. The approach this patch series takes is to perform CAR setup in the bootblock, and load the following stage (either romstage or verstage) from the boot media. This approach is not new, but has been done on our ARM ports for years. Since we will be adding .c files to the bootblock, it is prudent to use link-time garbage collection. This is also consistent to how we do things on other architectures. Unification FTW! Change-Id: I16b78456df56e0053984a9aca9367e2542adfdc9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11781 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>