coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2012-08-09	Synchronize rdtsc instructions	Stefan Reinauer
2012-08-07	Move cpus_ready_for_init() to AMD K8	Kyösti Mälkki
2012-08-01	Intel Sandybridge: add reserved memory as resources	Kyösti Mälkki
2012-07-31	Revert "Use broadcast SIPI to startup siblings"	Sven Schnelle
2012-07-31	Revert "remove CONFIG_SERIAL_CPU_INIT"	Sven Schnelle
2012-07-26	USBDEBUG: buffer up to 8 bytes	Sven Schnelle
2012-07-25	SMM: Fix state table for Intel Core2 CPUs	Stefan Reinauer
2012-07-25	Fix LAPIC timer on Ivy Bridge systems	Stefan Reinauer
2012-07-24	SMM: Fix state save map for sandybridge and TSEG	Duncan Laurie
2012-07-24	SMM: Add heap region and move C handler higher in region	Duncan Laurie
2012-07-24	Rename cache_lbmem() to cache_ramstage()	Stefan Reinauer
2012-07-24	MTRR: drop repetetive debug message	Stefan Reinauer
2012-07-23	Re-initialize Local APIC timer on APs	Stefan Reinauer
2012-07-16	Check for IORESOURCE_UMA_FB in MTRR setup	Kyösti Mälkki
2012-07-16	Define global uma_memory variables	Kyösti Mälkki
2012-07-12	Drop Kconfig VAR_MTRR_HOLE option	Kyösti Mälkki
2012-07-12	Fix stack assignment during CPU initialization	Sven Schnelle
2012-07-05	Only copy real-mode section of SIPI vector	Kyösti Mälkki
2012-07-05	Fix the CPU index parameter passed to secondary_cpu_init().	Kyösti Mälkki
2012-07-02	remove CONFIG_SERIAL_CPU_INIT	Sven Schnelle
2012-07-02	Use broadcast SIPI to startup siblings	Sven Schnelle
2012-06-12	udelay: add missing bus frequency	Sven Schnelle
2012-05-30	Fix the location of "Setting variable MTRR" printk.	Denis 'GNUtoo' Carikli
2012-05-08	Some more #if cleanup	Patrick Georgi
2012-05-08	Clean up #ifs	Patrick Georgi
2012-04-20	Revert wbind added to the reset_vector	Marc Jones
2012-04-11	Remove obsolete empy macro definition	Ron Minnich
2012-04-06	Fixes and Sandybridge support for lapic cpu init	Stefan Reinauer
2012-04-06	Add Sandybridge/Cougar Point support to SMM relocation handler	Stefan Reinauer
2012-04-06	Cache 8MB flash instead of 4MB	Stefan Reinauer
2012-04-05	Fix timer frequency detection on Sandybridge	Stefan Reinauer
2012-04-05	Invalidate cache before first jump	Stefan Reinauer
2012-04-05	Update documentation in smmrelocate.S to mention TSEG	Stefan Reinauer
2012-04-04	Add support to run SMM handler in TSEG instead of ASEG	Stefan Reinauer
2012-03-30	Make MTRR min hole alignment 64MB	Duncan Laurie
2012-03-30	Fix MB calculation in the reporting of the MTRR hole	Duncan Laurie
2012-03-30	MTRR: add alternate allocation method for odd memory maps	Duncan Laurie
2012-03-30	Add Kconfig options to enable TSEG and set a size	Duncan Laurie
2012-03-30	drop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not needed	Stefan Reinauer
2012-03-30	Add an option to keep the ROM cached after romstage	Stefan Reinauer
2012-03-25	Fix possible deadlock on SMP stop_this_cpu	Kyösti Mälkki
2012-03-16	ROMCC boards have no XIP limit	Patrick Georgi
2012-03-16	Fix address of IDT in real-mode entry	Kyösti Mälkki
2012-03-09	move console includes to central console/console.h	Stefan Reinauer
2012-03-07	Move C labels to start-of-line	Patrick Georgi
2012-02-17	Remove whitespace.	Patrick Georgi
2012-01-23	post code: Replaced hard-coded post code with macro	Vikram Narayanan
2012-01-21	trivial: spelling fixes in comments	Vikram Narayanan
2012-01-20	Leave SSE and MMX instructions enabled in coreboot	Stefan Reinauer
2012-01-10	MTRR: get physical address size from CPUID	Sven Schnelle