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coreboot
2560p
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autoport-hsw
broadwell_refcode
e6230
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haswell-mrc
hp820g1
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mec1322
Some coreboot project code with my work
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x86
Age
Commit message (
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Author
2012-03-30
Make MTRR min hole alignment 64MB
Duncan Laurie
2012-03-30
Fix MB calculation in the reporting of the MTRR hole
Duncan Laurie
2012-03-30
MTRR: add alternate allocation method for odd memory maps
Duncan Laurie
2012-03-30
Add Kconfig options to enable TSEG and set a size
Duncan Laurie
2012-03-30
drop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not needed
Stefan Reinauer
2012-03-30
Add an option to keep the ROM cached after romstage
Stefan Reinauer
2012-03-25
Fix possible deadlock on SMP stop_this_cpu
Kyösti Mälkki
2012-03-16
ROMCC boards have no XIP limit
Patrick Georgi
2012-03-16
Fix address of IDT in real-mode entry
Kyösti Mälkki
2012-03-09
move console includes to central console/console.h
Stefan Reinauer
2012-03-07
Move C labels to start-of-line
Patrick Georgi
2012-02-17
Remove whitespace.
Patrick Georgi
2012-01-23
post code: Replaced hard-coded post code with macro
Vikram Narayanan
2012-01-21
trivial: spelling fixes in comments
Vikram Narayanan
2012-01-20
Leave SSE and MMX instructions enabled in coreboot
Stefan Reinauer
2012-01-10
MTRR: get physical address size from CPUID
Sven Schnelle
2011-12-05
Bootblock does not need a unique boot_cpu()
Kyösti Mälkki
2011-11-24
Remove unused code files and cosmetic changes
Kyösti Mälkki
2011-11-22
Fix post_code in 16bit entry
Kyösti Mälkki
2011-11-01
remove trailing whitespace
Stefan Reinauer
2011-11-01
Remove XIP_ROM_BASE
Patrick Georgi
2011-10-28
Get rid of AUTO_XIP_ROM_BASE
Patrick Georgi
2011-10-15
SMM: Move wbinvd after pmode jump
Stefan Reinauer
2011-10-13
Load an IDT with NULL limit
Stefan Reinauer
2011-09-12
Miscellaneous AMD F14 warning fixes
efdesign98
2011-07-22
Add SSE3 dependent code
efdesign98
2011-07-04
Small SMM fixups
Rudolf Marek
2011-06-18
SMM: flush caches after disabling caching
Sven Schnelle
2011-06-15
SMM: don't overwrite SMM memory on resume
Sven Schnelle
2011-05-10
This replaces the fixed shift values in the apic timer init with macros.
Vikram Narayanan
2011-04-26
Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as an
Stefan Reinauer
2011-04-19
Fix some more misuses of ifdef/if defined
Stefan Reinauer
2011-04-14
drop half an uart8250 implementation from smiutil and use the common code
Stefan Reinauer
2011-04-14
earlymtrr.c: wipe some dead code, use names instead of numbers and some
Stefan Reinauer
2011-04-14
drop incorrectly used CONFIG_ROM_IMAGE_SIZE and unused CONFIG_ARCH
Stefan Reinauer
2011-04-11
Unify use of post_code
Alexandru Gagniuc
2011-01-19
Now that the VIA code is run above 1Meg (like other boards), it should
Kevin O'Connor
2010-12-18
SMM for AMD K8 Part 1/2
Stefan Reinauer
2010-12-18
Support Intel SCH (Poulsbo) and add iwave/iWRainbowG6 board
Patrick Georgi
2010-12-16
- Fix shortcoming in Kconfig when handling multiple "choice"s
Stefan Reinauer
2010-11-22
Printing coreboot debug messages on VGA console is pretty much useless, since
Stefan Reinauer
2010-11-13
MTRR related improvements for AMD family 10h and family 0Fh systems
Scott Duplichan
2010-10-20
Now that no boards set RAMBASE < 1M, get rid of some dead code. Trivial.
Myles Watson
2010-10-19
To reduce boot time, remove the double startup IPI and 10 ms delay from lapic...
Scott Duplichan
2010-09-30
Rename build system variables to be more intuitive, and
Patrick Georgi
2010-09-29
Forgot to 'svn add' src/cpu/x86/name (trivial).
Uwe Hermann
2010-09-27
Add a few missing license headers based on svn logs, and also add a
Uwe Hermann
2010-09-23
Whitespace/typo/cosmetic fixes (trivial).
Uwe Hermann
2010-09-09
Adapt comment, too. (trivial)
Patrick Georgi
2010-09-08
Make timer2 the default choice for TSC initialization.
Patrick Georgi
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