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path: root/src/cpu/x86
AgeCommit message (Expand)Author
2013-05-01x86: use boot state callbacks to disable rom cacheAaron Durbin
2013-04-04AMD: Drop six copies of wrmsr_amd and rdmsr_amdKyösti Mälkki
2013-04-01boot: add disable_cache_rom() functionAaron Durbin
2013-03-29x86: mtrr: optimize hole carving above 4GiBAaron Durbin
2013-03-29x86: mtrr: add hole punching supportAaron Durbin
2013-03-29x86: add rom cache variable MTRR index to tablesAaron Durbin
2013-03-29x86: mtrr: add CONFIG_CACHE_ROM supportAaron Durbin
2013-03-29mtrr: honor IORESOURCE_WRCOMBAaron Durbin
2013-03-29x86: add new mtrr implementationAaron Durbin
2013-03-22x86: unify amd and non-amd MTRR routinesAaron Durbin
2013-03-22x86: Unify arch/io.h and arch/romcc_io.hStefan Reinauer
2013-03-21ramstage: prepare for relocationAaron Durbin
2013-03-18SMM: link against libgccStefan Reinauer
2013-03-18haswell: lapic timer supportAaron Durbin
2013-03-18haswell: Use SMM ModulesAaron Durbin
2013-03-15Google Link: Add remaining code to support native graphicsRonald G. Minnich
2013-03-14x86: SMM Module SupportAaron Durbin
2013-03-14haswell: Add initial support for Haswell platformsAaron Durbin
2013-03-08Eliminate do_div().David Hendricks
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
2013-02-27smm: Update rev 0x30101 SMM revision save stateAaron Durbin
2013-02-11Intel: Replace MSR 0xcd with MSR_FSB_FREQPatrick Georgi
2012-12-06Unify assembler function handlingStefan Reinauer
2012-11-27Remove AMD special case for LAPIC based udelay()Patrick Georgi
2012-11-27intel/i82801ix: new southbridge, ICH9Patrick Georgi
2012-11-20secondary.S: Fix dropping ramstage.aStefan Reinauer
2012-11-20Make sure only one udelay function is availableStefan Reinauer
2012-11-13Clean up stack checking codeStefan Reinauer
2012-11-13clean up lapic_cpu_init.cStefan Reinauer
2012-11-13Pass the CPU index as a parameter to startup.Ronald G. Minnich
2012-11-13Support better tracking of AP stack usage.Ronald G. Minnich
2012-11-12Fix gcc-4.7 building problem.Han Shen
2012-08-09Synchronize rdtsc instructionsStefan Reinauer
2012-08-07Move cpus_ready_for_init() to AMD K8Kyösti Mälkki
2012-08-01Intel Sandybridge: add reserved memory as resourcesKyösti Mälkki
2012-07-31Revert "Use broadcast SIPI to startup siblings"Sven Schnelle
2012-07-31Revert "remove CONFIG_SERIAL_CPU_INIT"Sven Schnelle
2012-07-26USBDEBUG: buffer up to 8 bytesSven Schnelle
2012-07-25SMM: Fix state table for Intel Core2 CPUsStefan Reinauer
2012-07-25Fix LAPIC timer on Ivy Bridge systemsStefan Reinauer
2012-07-24SMM: Fix state save map for sandybridge and TSEGDuncan Laurie
2012-07-24SMM: Add heap region and move C handler higher in regionDuncan Laurie
2012-07-24Rename cache_lbmem() to cache_ramstage()Stefan Reinauer
2012-07-24MTRR: drop repetetive debug messageStefan Reinauer
2012-07-23Re-initialize Local APIC timer on APsStefan Reinauer
2012-07-16Check for IORESOURCE_UMA_FB in MTRR setupKyösti Mälkki
2012-07-16Define global uma_memory variablesKyösti Mälkki
2012-07-12Drop Kconfig VAR_MTRR_HOLE optionKyösti Mälkki
2012-07-12Fix stack assignment during CPU initializationSven Schnelle
2012-07-05Only copy real-mode section of SIPI vectorKyösti Mälkki
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